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huawei.com; dkim=none (message not signed) header.d=none;huawei.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT051.mail.protection.outlook.com (10.13.174.114) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4108.25 via Frontend Transport; Mon, 10 May 2021 16:13:55 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 10 May 2021 16:13:52 +0000 From: Xueming Li To: Chengchang Tang CC: Luca Boccassi , Min Hu , dpdk stable Date: Tue, 11 May 2021 00:00:57 +0800 Message-ID: <20210510160258.30982-108-xuemingl@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210510160258.30982-1-xuemingl@nvidia.com> References: <20210510160258.30982-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 769e3ba9-1e2b-424f-87f6-08d913ce9c2c X-MS-TrafficTypeDiagnostic: DM6PR12MB2892: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; 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PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(136003)(39860400002)(346002)(376002)(396003)(46966006)(36840700001)(1076003)(82310400003)(82740400003)(83380400001)(336012)(186003)(36906005)(426003)(316002)(7636003)(8676002)(356005)(54906003)(2616005)(36860700001)(16526019)(53546011)(8936002)(5660300002)(26005)(55016002)(6916009)(966005)(478600001)(6286002)(47076005)(36756003)(86362001)(2906002)(4326008)(7696005)(70206006)(70586007); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2021 16:13:55.2941 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 769e3ba9-1e2b-424f-87f6-08d913ce9c2c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT051.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB2892 Subject: [dpdk-stable] patch 'net/hns3: fix long task queue pairs reset time' has been queued to stable release 20.11.2 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Hi, FYI, your patch has been queued to stable release 20.11.2 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 05/12/21. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/steevenlee/dpdk This queued commit can be viewed at: https://github.com/steevenlee/dpdk/commit/a1b0bff2d5ac0df4c74ff05afaa97eeef799510b Thanks. Xueming Li --- >From a1b0bff2d5ac0df4c74ff05afaa97eeef799510b Mon Sep 17 00:00:00 2001 From: Chengchang Tang Date: Tue, 23 Mar 2021 21:45:56 +0800 Subject: [PATCH] net/hns3: fix long task queue pairs reset time Cc: Luca Boccassi [ upstream commit 6911e7c22c61a7071a534b198f79dc4c6d525445 ] Currently, the queue reset process needs to be performed one by one, which is inefficient. However, the queues reset in the same function is almost at the same stage. To optimize the queue reset process, a new function has been added to the firmware command HNS3_OPC_CFG_RST_TRIGGER to reset all queues in the same function at a time. And the related queue reset MBX message is adjusted in the same way too. Fixes: bba636698316 ("net/hns3: support Rx/Tx and related operations") Signed-off-by: Chengchang Tang Signed-off-by: Min Hu (Connor) --- drivers/net/hns3/hns3_cmd.h | 8 ++- drivers/net/hns3/hns3_rxtx.c | 125 ++++++++++++++++++++++++++++++----- 2 files changed, 114 insertions(+), 19 deletions(-) diff --git a/drivers/net/hns3/hns3_cmd.h b/drivers/net/hns3/hns3_cmd.h index 20c373590f..2d0bab000e 100644 --- a/drivers/net/hns3/hns3_cmd.h +++ b/drivers/net/hns3/hns3_cmd.h @@ -856,10 +856,16 @@ struct hns3_reset_tqp_queue_cmd { #define HNS3_CFG_RESET_MAC_B 3 #define HNS3_CFG_RESET_FUNC_B 7 +#define HNS3_CFG_RESET_RCB_B 1 struct hns3_reset_cmd { uint8_t mac_func_reset; uint8_t fun_reset_vfid; - uint8_t rsv[22]; + uint8_t fun_reset_rcb; + uint8_t rsv1; + uint16_t fun_reset_rcb_vqid_start; + uint16_t fun_reset_rcb_vqid_num; + uint8_t fun_reset_rcb_return_status; + uint8_t rsv2[15]; }; #define HNS3_QUERY_DEV_SPECS_BD_NUM 4 diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 2714f28f1d..6ba83f421c 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -629,10 +629,6 @@ hns3pf_reset_tqp(struct hns3_hw *hw, uint16_t queue_id) uint64_t end; int ret; - ret = hns3_tqp_enable(hw, queue_id, false); - if (ret) - return ret; - /* * In current version VF is not supported when PF is driven by DPDK * driver, all task queue pairs are mapped to PF function, so PF's queue @@ -679,11 +675,6 @@ hns3vf_reset_tqp(struct hns3_hw *hw, uint16_t queue_id) uint8_t msg_data[2]; int ret; - /* Disable VF's queue before send queue reset msg to PF */ - ret = hns3_tqp_enable(hw, queue_id, false); - if (ret) - return ret; - memcpy(msg_data, &queue_id, sizeof(uint16_t)); ret = hns3_send_mbx_msg(hw, HNS3_MBX_QUEUE_RESET, 0, msg_data, @@ -695,14 +686,105 @@ hns3vf_reset_tqp(struct hns3_hw *hw, uint16_t queue_id) } static int -hns3_reset_tqp(struct hns3_adapter *hns, uint16_t queue_id) +hns3_reset_rcb_cmd(struct hns3_hw *hw, uint8_t *reset_status) { - struct hns3_hw *hw = &hns->hw; + struct hns3_reset_cmd *req; + struct hns3_cmd_desc desc; + int ret; - if (hns->is_vf) - return hns3vf_reset_tqp(hw, queue_id); - else - return hns3pf_reset_tqp(hw, queue_id); + hns3_cmd_setup_basic_desc(&desc, HNS3_OPC_CFG_RST_TRIGGER, false); + req = (struct hns3_reset_cmd *)desc.data; + hns3_set_bit(req->mac_func_reset, HNS3_CFG_RESET_RCB_B, 1); + + /* + * The start qid should be the global qid of the first tqp of the + * function which should be reset in this port. Since our PF not + * support take over of VFs, so we only need to reset function 0, + * and its start qid is always 0. + */ + req->fun_reset_rcb_vqid_start = rte_cpu_to_le_16(0); + req->fun_reset_rcb_vqid_num = rte_cpu_to_le_16(hw->cfg_max_queues); + + ret = hns3_cmd_send(hw, &desc, 1); + if (ret) { + hns3_err(hw, "fail to send rcb reset cmd, ret = %d.", ret); + return ret; + } + + *reset_status = req->fun_reset_rcb_return_status; + return 0; +} + +static int +hns3pf_reset_all_tqps(struct hns3_hw *hw) +{ +#define HNS3_RESET_RCB_NOT_SUPPORT 0U +#define HNS3_RESET_ALL_TQP_SUCCESS 1U + uint8_t reset_status; + int ret; + int i; + + ret = hns3_reset_rcb_cmd(hw, &reset_status); + if (ret) + return ret; + + /* + * If the firmware version is low, it may not support the rcb reset + * which means reset all the tqps at a time. In this case, we should + * reset tqps one by one. + */ + if (reset_status == HNS3_RESET_RCB_NOT_SUPPORT) { + for (i = 0; i < hw->cfg_max_queues; i++) { + ret = hns3pf_reset_tqp(hw, i); + if (ret) { + hns3_err(hw, + "fail to reset tqp, queue_id = %d, ret = %d.", + i, ret); + return ret; + } + } + } else if (reset_status != HNS3_RESET_ALL_TQP_SUCCESS) { + hns3_err(hw, "fail to reset all tqps, reset_status = %u.", + reset_status); + return -EIO; + } + + return 0; +} + +static int +hns3vf_reset_all_tqps(struct hns3_hw *hw) +{ +#define HNS3VF_RESET_ALL_TQP_DONE 1U + uint8_t reset_status; + uint8_t msg_data[2]; + int ret; + int i; + + memset(msg_data, 0, sizeof(uint16_t)); + ret = hns3_send_mbx_msg(hw, HNS3_MBX_QUEUE_RESET, 0, msg_data, + sizeof(msg_data), true, &reset_status, + sizeof(reset_status)); + if (ret) { + hns3_err(hw, "fail to send rcb reset mbx, ret = %d.", ret); + return ret; + } + + if (reset_status == HNS3VF_RESET_ALL_TQP_DONE) + return 0; + + /* + * If the firmware version or kernel PF version is low, it may not + * support the rcb reset which means reset all the tqps at a time. + * In this case, we should reset tqps one by one. + */ + for (i = 1; i < hw->cfg_max_queues; i++) { + ret = hns3vf_reset_tqp(hw, i); + if (ret) + return ret; + } + + return 0; } int @@ -711,14 +793,21 @@ hns3_reset_all_tqps(struct hns3_adapter *hns) struct hns3_hw *hw = &hns->hw; int ret, i; + /* Disable all queues before reset all queues */ for (i = 0; i < hw->cfg_max_queues; i++) { - ret = hns3_reset_tqp(hns, i); + ret = hns3_tqp_enable(hw, i, false); if (ret) { - hns3_err(hw, "Failed to reset No.%d queue: %d", i, ret); + hns3_err(hw, + "fail to disable tqps before tqps reset, ret = %d.", + ret); return ret; } } - return 0; + + if (hns->is_vf) + return hns3vf_reset_all_tqps(hw); + else + return hns3pf_reset_all_tqps(hw); } static int -- 2.25.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2021-05-10 23:59:29.424338600 +0800 +++ 0109-net-hns3-fix-long-task-queue-pairs-reset-time.patch 2021-05-10 23:59:26.500000000 +0800 @@ -1 +1 @@ -From 6911e7c22c61a7071a534b198f79dc4c6d525445 Mon Sep 17 00:00:00 2001 +From a1b0bff2d5ac0df4c74ff05afaa97eeef799510b Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Luca Boccassi + +[ upstream commit 6911e7c22c61a7071a534b198f79dc4c6d525445 ] @@ -14 +16,0 @@ -Cc: stable@dpdk.org @@ -24 +26 @@ -index e704d0c40b..30aca82d32 100644 +index 20c373590f..2d0bab000e 100644 @@ -27 +29 @@ -@@ -933,10 +933,16 @@ struct hns3_reset_tqp_queue_cmd { +@@ -856,10 +856,16 @@ struct hns3_reset_tqp_queue_cmd { @@ -46 +48 @@ -index 5bb35e14a1..ce5d852773 100644 +index 2714f28f1d..6ba83f421c 100644