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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT006.mail.protection.outlook.com (10.13.177.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4108.25 via Frontend Transport; Mon, 10 May 2021 16:05:24 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 10 May 2021 16:05:22 +0000 From: Xueming Li To: Viacheslav Ovsiienko CC: Luca Boccassi , Matan Azrad , "dpdk stable" Date: Mon, 10 May 2021 23:59:30 +0800 Message-ID: <20210510160258.30982-21-xuemingl@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210510160258.30982-1-xuemingl@nvidia.com> References: <20210510160258.30982-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 1f96ddb7-0f9b-4fa4-c41b-08d913cd6bdc X-MS-TrafficTypeDiagnostic: MN2PR12MB3805: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; 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PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(396003)(136003)(39860400002)(376002)(346002)(36840700001)(46966006)(6666004)(2616005)(6286002)(1076003)(53546011)(83380400001)(4326008)(36756003)(478600001)(47076005)(2906002)(5660300002)(54906003)(356005)(7696005)(316002)(82740400003)(37006003)(86362001)(36860700001)(36906005)(6636002)(6862004)(7636003)(186003)(55016002)(16526019)(966005)(8676002)(70586007)(70206006)(82310400003)(336012)(26005)(15650500001)(426003)(8936002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2021 16:05:24.6420 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1f96ddb7-0f9b-4fa4-c41b-08d913cd6bdc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT006.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3805 Subject: [dpdk-stable] patch 'net/mlx5: fix UAR allocation diagnostics messages' has been queued to stable release 20.11.2 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Hi, FYI, your patch has been queued to stable release 20.11.2 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 05/12/21. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/steevenlee/dpdk This queued commit can be viewed at: https://github.com/steevenlee/dpdk/commit/82f21305c4abbc39a8e3cece20919aacd061d01d Thanks. Xueming Li --- >From 82f21305c4abbc39a8e3cece20919aacd061d01d Mon Sep 17 00:00:00 2001 From: Viacheslav Ovsiienko Date: Wed, 24 Feb 2021 10:17:35 +0200 Subject: [PATCH] net/mlx5: fix UAR allocation diagnostics messages Cc: Luca Boccassi [ upstream commit 09d196c0a0797813c0c608f303c9ebbe58656fbe ] Depending on kernel capabilities and rdma-core version the mapping of UAR (User Access Region) of desired memory caching type (non-cached or write combining) might fail. The PMD implements the flexible strategy of UAR mapping, alternating the type of caching to succeed. During this process the failure diagnostics messages are emitted. These messages are merely diagnostics ones and the logging level should be adjusted to DEBUG. Fixes: a0bfe9d56f74 ("net/mlx5: fix UAR memory mapping type") Signed-off-by: Viacheslav Ovsiienko Acked-by: Matan Azrad --- drivers/net/mlx5/mlx5.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index bdb446d2d2..b8f31497b2 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -767,7 +767,7 @@ mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh, * the UAR mapping type into account on UAR setup * on queue creation. */ - DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (BF)"); + DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (BF)"); uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC; sh->tx_uar = mlx5_glue->devx_alloc_uar (sh->ctx, uar_mapping); @@ -780,7 +780,7 @@ mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh, * If Verbs/kernel does not support "Non-Cached" * try the "Write-Combining". */ - DRV_LOG(WARNING, "Failed to allocate Tx DevX UAR (NC)"); + DRV_LOG(DEBUG, "Failed to allocate Tx DevX UAR (NC)"); uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF; sh->tx_uar = mlx5_glue->devx_alloc_uar (sh->ctx, uar_mapping); @@ -799,7 +799,7 @@ mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh, * IB device context, on context closure all UARs * will be freed, should be no memory/object leakage. */ - DRV_LOG(WARNING, "Retrying to allocate Tx DevX UAR"); + DRV_LOG(DEBUG, "Retrying to allocate Tx DevX UAR"); sh->tx_uar = NULL; } /* Check whether we finally succeeded with valid UAR allocation. */ @@ -820,7 +820,7 @@ mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh, * should be no datapath noticeable impact, * can try "Non-Cached" mapping safely. */ - DRV_LOG(WARNING, "Failed to allocate Rx DevX UAR (BF)"); + DRV_LOG(DEBUG, "Failed to allocate Rx DevX UAR (BF)"); uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC; sh->devx_rx_uar = mlx5_glue->devx_alloc_uar (sh->ctx, uar_mapping); @@ -839,7 +839,7 @@ mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh, * IB device context, on context closure all UARs * will be freed, should be no memory/object leakage. */ - DRV_LOG(WARNING, "Retrying to allocate Rx DevX UAR"); + DRV_LOG(DEBUG, "Retrying to allocate Rx DevX UAR"); sh->devx_rx_uar = NULL; } /* Check whether we finally succeeded with valid UAR allocation. */ -- 2.25.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2021-05-10 23:59:27.261623800 +0800 +++ 0022-net-mlx5-fix-UAR-allocation-diagnostics-messages.patch 2021-05-10 23:59:26.350000000 +0800 @@ -1 +1 @@ -From 09d196c0a0797813c0c608f303c9ebbe58656fbe Mon Sep 17 00:00:00 2001 +From 82f21305c4abbc39a8e3cece20919aacd061d01d Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Luca Boccassi + +[ upstream commit 09d196c0a0797813c0c608f303c9ebbe58656fbe ] @@ -15 +17,0 @@ -Cc: stable@dpdk.org @@ -24 +26 @@ -index aae2ef9af7..4ee0005a5c 100644 +index bdb446d2d2..b8f31497b2 100644 @@ -27 +29 @@ -@@ -768,7 +768,7 @@ mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh, +@@ -767,7 +767,7 @@ mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh, @@ -36 +38 @@ -@@ -781,7 +781,7 @@ mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh, +@@ -780,7 +780,7 @@ mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh, @@ -45 +47 @@ -@@ -800,7 +800,7 @@ mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh, +@@ -799,7 +799,7 @@ mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh, @@ -54 +56 @@ -@@ -821,7 +821,7 @@ mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh, +@@ -820,7 +820,7 @@ mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh, @@ -63 +65 @@ -@@ -840,7 +840,7 @@ mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh, +@@ -839,7 +839,7 @@ mlx5_alloc_rxtx_uars(struct mlx5_dev_ctx_shared *sh,