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broadcom.com; dkim=none (message not signed) header.d=none;broadcom.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT024.mail.protection.outlook.com (10.13.177.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4108.25 via Frontend Transport; Mon, 10 May 2021 16:08:30 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 10 May 2021 16:08:24 +0000 From: Xueming Li To: Kalesh AP CC: Luca Boccassi , Somnath Kotur , Ajit Khaparde , dpdk stable Date: Tue, 11 May 2021 00:00:02 +0800 Message-ID: <20210510160258.30982-53-xuemingl@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210510160258.30982-1-xuemingl@nvidia.com> References: <20210510160258.30982-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9312f9f4-ca4e-457a-8aae-08d913cdda95 X-MS-TrafficTypeDiagnostic: BYAPR12MB3624: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; 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PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(376002)(346002)(39860400002)(396003)(136003)(36840700001)(46966006)(86362001)(36860700001)(36756003)(53546011)(478600001)(8676002)(55016002)(7636003)(83380400001)(2906002)(966005)(70206006)(336012)(70586007)(6666004)(6916009)(426003)(5660300002)(2616005)(7696005)(316002)(82740400003)(356005)(82310400003)(26005)(1076003)(186003)(16526019)(4326008)(54906003)(47076005)(6286002)(36906005)(8936002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2021 16:08:30.4343 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9312f9f4-ca4e-457a-8aae-08d913cdda95 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT024.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR12MB3624 Subject: [dpdk-stable] patch 'net/bnxt: fix firmware fatal error handling' has been queued to stable release 20.11.2 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Hi, FYI, your patch has been queued to stable release 20.11.2 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 05/12/21. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/steevenlee/dpdk This queued commit can be viewed at: https://github.com/steevenlee/dpdk/commit/3fd1f9e8ec81d6469633e7298d119542b129e60d Thanks. Xueming Li --- >From 3fd1f9e8ec81d6469633e7298d119542b129e60d Mon Sep 17 00:00:00 2001 From: Kalesh AP Date: Wed, 24 Feb 2021 21:25:51 +0530 Subject: [PATCH] net/bnxt: fix firmware fatal error handling Cc: Luca Boccassi [ upstream commit 94131e4ab74728da994d5179052bb30c3c76910c ] During some fatal firmware error conditions, the PCI config space register 0x2e which normally contains the subsystem ID will become 0xffff. This register will revert back to the normal value after the chip has completed core reset. If we detect this condition, we can poll this config register immediately for the value to revert. Because we use config read cycles to poll this register, there is no possibility of Master Abort if we happen to read it during core reset. This speeds up recovery significantly as we don't have to wait for the conservative min_time before polling to see if the firmware has come out of reset. As soon as this register changes value we can proceed to re-initialize the device. Fixes: df6cd7c1f73a ("net/bnxt: handle reset notify async event from FW") Signed-off-by: Kalesh AP Reviewed-by: Somnath Kotur Reviewed-by: Ajit Khaparde --- drivers/net/bnxt/bnxt_ethdev.c | 56 ++++++++++++++++++++++++++++++++-- drivers/net/bnxt/bnxt_util.h | 2 ++ 2 files changed, 56 insertions(+), 2 deletions(-) diff --git a/drivers/net/bnxt/bnxt_ethdev.c b/drivers/net/bnxt/bnxt_ethdev.c index 3aa346d45c..f0de861798 100644 --- a/drivers/net/bnxt/bnxt_ethdev.c +++ b/drivers/net/bnxt/bnxt_ethdev.c @@ -3682,6 +3682,32 @@ static void bnxt_dev_cleanup(struct bnxt *bp) bnxt_uninit_resources(bp, true); } +static int +bnxt_check_fw_reset_done(struct bnxt *bp) +{ + int timeout = bp->fw_reset_max_msecs; + uint16_t val = 0; + int rc; + + do { + rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET); + if (rc < 0) { + PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET); + return rc; + } + if (val != 0xffff) + break; + rte_delay_ms(1); + } while (timeout--); + + if (val == 0xffff) { + PMD_DRV_LOG(ERR, "Firmware reset aborted, PCI config space invalid\n"); + return -1; + } + + return 0; +} + static int bnxt_restore_vlan_filters(struct bnxt *bp) { struct rte_eth_dev *dev = bp->eth_dev; @@ -3778,6 +3804,13 @@ static void bnxt_dev_recover(void *arg) int timeout = bp->fw_reset_max_msecs; int rc = 0; + + if (!bp->fw_reset_min_msecs) { + rc = bnxt_check_fw_reset_done(bp); + if (rc) + goto err; + } + /* Clear Error flag so that device re-init should happen */ bp->flags &= ~BNXT_FLAG_FATAL_ERROR; @@ -3826,14 +3859,33 @@ err: void bnxt_dev_reset_and_resume(void *arg) { struct bnxt *bp = arg; + uint32_t us = US_PER_MS * bp->fw_reset_min_msecs; + uint16_t val = 0; int rc; bnxt_dev_cleanup(bp); bnxt_wait_for_device_shutdown(bp); - rc = rte_eal_alarm_set(US_PER_MS * bp->fw_reset_min_msecs, - bnxt_dev_recover, (void *)bp); + /* During some fatal firmware error conditions, the PCI config space + * register 0x2e which normally contains the subsystem ID will become + * 0xffff. This register will revert back to the normal value after + * the chip has completed core reset. If we detect this condition, + * we can poll this config register immediately for the value to revert. + */ + if (bp->flags & BNXT_FLAG_FATAL_ERROR) { + rc = rte_pci_read_config(bp->pdev, &val, sizeof(val), PCI_SUBSYSTEM_ID_OFFSET); + if (rc < 0) { + PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_SUBSYSTEM_ID_OFFSET); + return; + } + if (val == 0xffff) { + bp->fw_reset_min_msecs = 0; + us = 1; + } + } + + rc = rte_eal_alarm_set(us, bnxt_dev_recover, (void *)bp); if (rc) PMD_DRV_LOG(ERR, "Error setting recovery alarm"); } diff --git a/drivers/net/bnxt/bnxt_util.h b/drivers/net/bnxt/bnxt_util.h index a15b3a1a95..68665196c3 100644 --- a/drivers/net/bnxt/bnxt_util.h +++ b/drivers/net/bnxt/bnxt_util.h @@ -10,6 +10,8 @@ #define BIT(n) (1UL << (n)) #endif /* BIT */ +#define PCI_SUBSYSTEM_ID_OFFSET 0x2e + int bnxt_check_zero_bytes(const uint8_t *bytes, int len); void bnxt_eth_hw_addr_random(uint8_t *mac_addr); -- 2.25.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2021-05-10 23:59:28.035049600 +0800 +++ 0054-net-bnxt-fix-firmware-fatal-error-handling.patch 2021-05-10 23:59:26.400000000 +0800 @@ -1 +1 @@ -From 94131e4ab74728da994d5179052bb30c3c76910c Mon Sep 17 00:00:00 2001 +From 3fd1f9e8ec81d6469633e7298d119542b129e60d Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Luca Boccassi + +[ upstream commit 94131e4ab74728da994d5179052bb30c3c76910c ] @@ -19 +21,0 @@ -Cc: stable@dpdk.org @@ -30 +32 @@ -index 9e0ec46403..67ff800da5 100644 +index 3aa346d45c..f0de861798 100644 @@ -33 +35 @@ -@@ -3743,6 +3743,32 @@ static void bnxt_dev_cleanup(struct bnxt *bp) +@@ -3682,6 +3682,32 @@ static void bnxt_dev_cleanup(struct bnxt *bp) @@ -66 +68,2 @@ -@@ -3840,6 +3866,13 @@ static void bnxt_dev_recover(void *arg) +@@ -3778,6 +3804,13 @@ static void bnxt_dev_recover(void *arg) + int timeout = bp->fw_reset_max_msecs; @@ -69 +71,0 @@ - pthread_mutex_lock(&bp->err_recovery_lock); @@ -80 +82 @@ -@@ -3891,14 +3924,33 @@ err: +@@ -3826,14 +3859,33 @@ err: @@ -117 +119 @@ -index 8de55e1038..64e97eed15 100644 +index a15b3a1a95..68665196c3 100644