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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT021.mail.protection.outlook.com (10.13.177.114) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4108.25 via Frontend Transport; Mon, 10 May 2021 16:09:28 +0000 Received: from nvidia.com (172.20.145.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 10 May 2021 16:09:25 +0000 From: Xueming Li To: Viacheslav Ovsiienko CC: Luca Boccassi , Matan Azrad , Ori Kam , dpdk stable Date: Tue, 11 May 2021 00:00:13 +0800 Message-ID: <20210510160258.30982-64-xuemingl@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210510160258.30982-1-xuemingl@nvidia.com> References: <20210510160258.30982-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.145.6] X-ClientProxiedBy: HQMAIL111.nvidia.com (172.20.187.18) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: b4be016c-a942-4b5f-85e2-08d913cdfd06 X-MS-TrafficTypeDiagnostic: DM6PR12MB3482: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:9508; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 May 2021 16:09:28.2183 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b4be016c-a942-4b5f-85e2-08d913cdfd06 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT021.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3482 Subject: [dpdk-stable] patch 'vdpa/mlx5: support timestamp format' has been queued to stable release 20.11.2 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Hi, FYI, your patch has been queued to stable release 20.11.2 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 05/12/21. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/steevenlee/dpdk This queued commit can be viewed at: https://github.com/steevenlee/dpdk/commit/cd5184145e57822667e7b1bb534ebe28e9b90413 Thanks. Xueming Li --- >From cd5184145e57822667e7b1bb534ebe28e9b90413 Mon Sep 17 00:00:00 2001 From: Viacheslav Ovsiienko Date: Sun, 14 Mar 2021 12:13:00 +0000 Subject: [PATCH] vdpa/mlx5: support timestamp format Cc: Luca Boccassi [ upstream commit 044423c4db97ca1911d0dcd06bc21f3fe84ed8c7 ] This patch adds support for the timestamp format settings for the receive and send queues. If the firmware version x.30.1000 or above is installed and the NIC timestamps are configured with the real-time format, the default zero values for newly added fields cause the queue creation to fail. The patch queries the timestamp formats supported by the hardware and sets the configuration values in queue context accordingly. Fixes: 95276abaaf0a ("vdpa/mlx5: introduce Mellanox vDPA driver") Signed-off-by: Viacheslav Ovsiienko Acked-by: Matan Azrad Acked-by: Ori Kam --- drivers/vdpa/mlx5/mlx5_vdpa.c | 1 + drivers/vdpa/mlx5/mlx5_vdpa.h | 1 + drivers/vdpa/mlx5/mlx5_vdpa_event.c | 2 ++ 3 files changed, 4 insertions(+) diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.c b/drivers/vdpa/mlx5/mlx5_vdpa.c index 0b2f1ab68e..228f5f59d2 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa.c @@ -735,6 +735,7 @@ mlx5_vdpa_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, priv->caps = attr.vdpa; priv->log_max_rqt_size = attr.log_max_rqt_size; priv->num_lag_ports = attr.num_lag_ports; + priv->qp_ts_format = attr.qp_ts_format; if (attr.num_lag_ports == 0) priv->num_lag_ports = 1; priv->ctx = ctx; diff --git a/drivers/vdpa/mlx5/mlx5_vdpa.h b/drivers/vdpa/mlx5/mlx5_vdpa.h index d039ada65b..fefc7cfdad 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa.h +++ b/drivers/vdpa/mlx5/mlx5_vdpa.h @@ -154,6 +154,7 @@ struct mlx5_vdpa_priv { struct mlx5_devx_obj *tiss[16]; /* TIS list for each LAG port. */ uint16_t nr_virtqs; uint8_t num_lag_ports; + uint8_t qp_ts_format; uint64_t features; /* Negotiated features. */ uint16_t log_max_rqt_size; struct mlx5_vdpa_steer steer; diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_event.c b/drivers/vdpa/mlx5/mlx5_vdpa_event.c index 3aeaeb893f..266cd8e57c 100644 --- a/drivers/vdpa/mlx5/mlx5_vdpa_event.c +++ b/drivers/vdpa/mlx5/mlx5_vdpa_event.c @@ -659,6 +659,7 @@ mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv, uint16_t desc_n, if (mlx5_vdpa_cq_create(priv, log_desc_n, callfd, &eqp->cq)) return -1; attr.pd = priv->pdn; + attr.ts_format = mlx5_ts_format_conv(priv->qp_ts_format); eqp->fw_qp = mlx5_devx_cmd_create_qp(priv->ctx, &attr); if (!eqp->fw_qp) { DRV_LOG(ERR, "Failed to create FW QP(%u).", rte_errno); @@ -689,6 +690,7 @@ mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv, uint16_t desc_n, attr.wq_umem_offset = 0; attr.dbr_umem_id = eqp->umem_obj->umem_id; attr.dbr_address = (1 << log_desc_n) * MLX5_WSEG_SIZE; + attr.ts_format = mlx5_ts_format_conv(priv->qp_ts_format); eqp->sw_qp = mlx5_devx_cmd_create_qp(priv->ctx, &attr); if (!eqp->sw_qp) { DRV_LOG(ERR, "Failed to create SW QP(%u).", rte_errno); -- 2.25.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2021-05-10 23:59:28.316498500 +0800 +++ 0065-vdpa-mlx5-support-timestamp-format.patch 2021-05-10 23:59:26.420000000 +0800 @@ -1 +1 @@ -From 044423c4db97ca1911d0dcd06bc21f3fe84ed8c7 Mon Sep 17 00:00:00 2001 +From cd5184145e57822667e7b1bb534ebe28e9b90413 Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Luca Boccassi + +[ upstream commit 044423c4db97ca1911d0dcd06bc21f3fe84ed8c7 ] @@ -16 +18,0 @@ -Cc: stable@dpdk.org @@ -28 +30 @@ -index 5755a68ec4..898e50f807 100644 +index 0b2f1ab68e..228f5f59d2 100644 @@ -31 +33 @@ -@@ -745,6 +745,7 @@ mlx5_vdpa_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, +@@ -735,6 +735,7 @@ mlx5_vdpa_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, @@ -40 +42 @@ -index 98c71aad4c..d93b430c97 100644 +index d039ada65b..fefc7cfdad 100644 @@ -43 +45 @@ -@@ -152,6 +152,7 @@ struct mlx5_vdpa_priv { +@@ -154,6 +154,7 @@ struct mlx5_vdpa_priv { @@ -52 +54 @@ -index 86adc864f5..7cf2c76e70 100644 +index 3aeaeb893f..266cd8e57c 100644 @@ -55 +57 @@ -@@ -662,6 +662,7 @@ mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv, uint16_t desc_n, +@@ -659,6 +659,7 @@ mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv, uint16_t desc_n, @@ -63 +65 @@ -@@ -692,6 +693,7 @@ mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv, uint16_t desc_n, +@@ -689,6 +690,7 @@ mlx5_vdpa_event_qp_create(struct mlx5_vdpa_priv *priv, uint16_t desc_n,