From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0CA56A0546 for ; Wed, 26 May 2021 11:28:30 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id C684E4003F; Wed, 26 May 2021 11:28:29 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mails.dpdk.org (Postfix) with ESMTP id 2ED1D4003F for ; Wed, 26 May 2021 11:28:26 +0200 (CEST) IronPort-SDR: nZsZkbpZxluHxLtcpJLAjlPlcZPkCaMLsmwtfvk6Eism5D/Fm7EteDbHN8/7syao1BrGLCXBRj P38f40wIty2w== X-IronPort-AV: E=McAfee;i="6200,9189,9995"; a="266318587" X-IronPort-AV: E=Sophos;i="5.82,331,1613462400"; d="scan'208";a="266318587" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 May 2021 02:28:25 -0700 IronPort-SDR: pci4mjec9SbUsazisKriQZXdJ3al6v/ajgIHGHoPlEme+2N1b3ZRHKsjQP+04e3gEm2Ay6IWtj 0K5LzMwJ0HDA== X-IronPort-AV: E=Sophos;i="5.82,331,1613462400"; d="scan'208";a="476850024" Received: from vfio-vm.cd.intel.com ([10.240.178.198]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 May 2021 02:28:24 -0700 From: Jie Wang To: stable@dpdk.org Cc: Jie Wang , Murphy Yang Date: Wed, 26 May 2021 09:15:19 +0000 Message-Id: <20210526091519.28371-1-jie1x.wang@intel.com> X-Mailer: git-send-email 2.17.1 Subject: [dpdk-stable] [PATCH 19.11] net/i40e: fix flow director config after flow validate X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" [ upstream commit 4a072ad434426ebfb5a6120858a971b54e7d2204 ] The configuration of FDIR input set should not be set during flow validate. It should be set when flow create. Fixes: fe5d0e85b713 ("net/i40e: fix flow director flex configuration") Fixes: 15018d79f0be ("net/i40e: add FDIR support for GTP-C and GTP-U") Cc: stable@dpdk.org Signed-off-by: Murphy Yang Acked-by: Beilei Xing Signed-off-by: Jie Wang --- drivers/net/i40e/i40e_ethdev.h | 1 + drivers/net/i40e/i40e_fdir.c | 90 ++++++++++++++++++++++++++++++++ drivers/net/i40e/i40e_flow.c | 95 +++------------------------------- 3 files changed, 98 insertions(+), 88 deletions(-) diff --git a/drivers/net/i40e/i40e_ethdev.h b/drivers/net/i40e/i40e_ethdev.h index 91d6830a3c..472da7a059 100644 --- a/drivers/net/i40e/i40e_ethdev.h +++ b/drivers/net/i40e/i40e_ethdev.h @@ -558,6 +558,7 @@ struct i40e_fdir_flow_ext { uint8_t is_vf; /* 1 for VF, 0 for port dev */ uint16_t dst_id; /* VF ID, available when is_vf is 1*/ bool inner_ip; /* If there is inner ip */ + uint64_t input_set; enum i40e_fdir_ip_type iip_type; /* ip type for inner ip */ bool customized_pctype; /* If customized pctype is used */ bool pkt_template; /* If raw packet template is used */ diff --git a/drivers/net/i40e/i40e_fdir.c b/drivers/net/i40e/i40e_fdir.c index fb9f2c0fce..0f4dbe6d1e 100644 --- a/drivers/net/i40e/i40e_fdir.c +++ b/drivers/net/i40e/i40e_fdir.c @@ -1697,6 +1697,89 @@ i40e_flow_set_fdir_flex_msk(struct i40e_pf *pf, pf->fdir.flex_mask_flag[pctype] = 1; } +static int +i40e_flow_set_fdir_inset(struct i40e_pf *pf, + enum i40e_filter_pctype pctype, + uint64_t input_set) +{ + struct i40e_hw *hw = I40E_PF_TO_HW(pf); + uint64_t inset_reg = 0; + uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0}; + int i, num; + + /* Check if the input set is valid */ + if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR, + input_set) != 0) { + PMD_DRV_LOG(ERR, "Invalid input set"); + return -EINVAL; + } + + /* Check if the configuration is conflicted */ + if (pf->fdir.inset_flag[pctype] && + memcmp(&pf->fdir.input_set[pctype], + &input_set, sizeof(uint64_t))) { + PMD_DRV_LOG(ERR, "Conflict with the first rule's input set."); + return -EINVAL; + } + + if (pf->fdir.inset_flag[pctype] && + !memcmp(&pf->fdir.input_set[pctype], + &input_set, sizeof(uint64_t))) + return 0; + + num = i40e_generate_inset_mask_reg(input_set, mask_reg, + I40E_INSET_MASK_NUM_REG); + if (num < 0) { + PMD_DRV_LOG(ERR, "Invalid pattern mask."); + return -EINVAL; + } + + if (pf->support_multi_driver) { + for (i = 0; i < num; i++) + if (i40e_read_rx_ctl(hw, + I40E_GLQF_FD_MSK(i, pctype)) != + mask_reg[i]) { + PMD_DRV_LOG(ERR, "Input set setting is not" + " supported with" + " `support-multi-driver`" + " enabled!"); + return -EPERM; + } + for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) + if (i40e_read_rx_ctl(hw, + I40E_GLQF_FD_MSK(i, pctype)) != 0) { + PMD_DRV_LOG(ERR, "Input set setting is not" + " supported with" + " `support-multi-driver`" + " enabled!"); + return -EPERM; + } + + } else { + for (i = 0; i < num; i++) + i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype), + mask_reg[i]); + /*clear unused mask registers of the pctype */ + for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) + i40e_check_write_reg(hw, + I40E_GLQF_FD_MSK(i, pctype), 0); + } + + inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set); + + i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0), + (uint32_t)(inset_reg & UINT32_MAX)); + i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1), + (uint32_t)((inset_reg >> + I40E_32_BIT_WIDTH) & UINT32_MAX)); + + I40E_WRITE_FLUSH(hw); + + pf->fdir.input_set[pctype] = input_set; + pf->fdir.inset_flag[pctype] = 1; + return 0; +} + /** * i40e_flow_add_del_fdir_filter - add or remove a flow director filter. * @pf: board private structure @@ -1765,6 +1848,13 @@ i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev, return -EINVAL; } + if (add && !filter->input.flow_ext.customized_pctype) { + ret = i40e_flow_set_fdir_inset(pf, pctype, + filter->input.flow_ext.input_set); + if (ret < 0) + return ret; + } + memset(pkt, 0, I40E_FDIR_PKT_LEN); ret = i40e_flow_fdir_construct_pkt(pf, &filter->input, pkt); diff --git a/drivers/net/i40e/i40e_flow.c b/drivers/net/i40e/i40e_flow.c index 4f5f31c802..809293860f 100644 --- a/drivers/net/i40e/i40e_flow.c +++ b/drivers/net/i40e/i40e_flow.c @@ -2175,83 +2175,6 @@ i40e_flow_check_raw_item(const struct rte_flow_item *item, return 0; } -static int -i40e_flow_set_fdir_inset(struct i40e_pf *pf, - enum i40e_filter_pctype pctype, - uint64_t input_set) -{ - struct i40e_hw *hw = I40E_PF_TO_HW(pf); - uint64_t inset_reg = 0; - uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0}; - int i, num; - - /* Check if the input set is valid */ - if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR, - input_set) != 0) { - PMD_DRV_LOG(ERR, "Invalid input set"); - return -EINVAL; - } - - /* Check if the configuration is conflicted */ - if (pf->fdir.inset_flag[pctype] && - memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t))) - return -1; - - if (pf->fdir.inset_flag[pctype] && - !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t))) - return 0; - - num = i40e_generate_inset_mask_reg(input_set, mask_reg, - I40E_INSET_MASK_NUM_REG); - if (num < 0) - return -EINVAL; - - if (pf->support_multi_driver) { - for (i = 0; i < num; i++) - if (i40e_read_rx_ctl(hw, - I40E_GLQF_FD_MSK(i, pctype)) != - mask_reg[i]) { - PMD_DRV_LOG(ERR, "Input set setting is not" - " supported with" - " `support-multi-driver`" - " enabled!"); - return -EPERM; - } - for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) - if (i40e_read_rx_ctl(hw, - I40E_GLQF_FD_MSK(i, pctype)) != 0) { - PMD_DRV_LOG(ERR, "Input set setting is not" - " supported with" - " `support-multi-driver`" - " enabled!"); - return -EPERM; - } - - } else { - for (i = 0; i < num; i++) - i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype), - mask_reg[i]); - /*clear unused mask registers of the pctype */ - for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) - i40e_check_write_reg(hw, - I40E_GLQF_FD_MSK(i, pctype), 0); - } - - inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set); - - i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0), - (uint32_t)(inset_reg & UINT32_MAX)); - i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1), - (uint32_t)((inset_reg >> - I40E_32_BIT_WIDTH) & UINT32_MAX)); - - I40E_WRITE_FLUSH(hw); - - pf->fdir.input_set[pctype] = input_set; - pf->fdir.inset_flag[pctype] = 1; - return 0; -} - static uint8_t i40e_flow_fdir_get_pctype_value(struct i40e_pf *pf, enum rte_flow_item_type item_type, @@ -2888,18 +2811,14 @@ i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev, /* If customized pctype is not used, set fdir configuration.*/ if (!filter->input.flow_ext.customized_pctype) { - ret = i40e_flow_set_fdir_inset(pf, pctype, input_set); - if (ret == -1) { - rte_flow_error_set(error, EINVAL, - RTE_FLOW_ERROR_TYPE_ITEM, item, - "Conflict with the first rule's input set."); - return -rte_errno; - } else if (ret == -EINVAL) { - rte_flow_error_set(error, EINVAL, - RTE_FLOW_ERROR_TYPE_ITEM, item, - "Invalid pattern mask."); - return -rte_errno; + /* Check if the input set is valid */ + if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR, + input_set) != 0) { + PMD_DRV_LOG(ERR, "Invalid input set"); + return -EINVAL; } + + filter->input.flow_ext.input_set = input_set; } filter->input.pctype = pctype; -- 2.17.1