From: Haiyue Wang <haiyue.wang@intel.com>
To: stable@dpdk.org
Cc: bluca@debian.org, xuemingl@nvidia.com, thomas@monjalon.net,
christian.ehrhardt@canonical.com, ktraynor@redhat.com,
qi.z.zhang@intel.com, haiyue.wang@intel.com,
Shay Amir <shay.amir@intel.com>,
Qiming Yang <qiming.yang@intel.com>
Subject: [dpdk-stable] [PATCH 20.11 v2 01/18] net/ice/base: align add VSI and update VSI AQ command buffer
Date: Fri, 11 Jun 2021 15:15:13 +0800 [thread overview]
Message-ID: <20210611071531.48411-2-haiyue.wang@intel.com> (raw)
In-Reply-To: <20210611071531.48411-1-haiyue.wang@intel.com>
From: Qi Zhang <qi.z.zhang@intel.com>
[ upstream commit 9ea028123a0bef9f6bbf5dd1a5250b9bfa63c1ea ]
Aligned the buffer the following admin commands to their new
definitions:
* 0x210 = add_vsi
* 0x211 = update_vsi
Signed-off-by: Shay Amir <shay.amir@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/ice/base/ice_adminq_cmd.h | 209 +++++++++++++-------------
drivers/net/ice/ice_ethdev.c | 88 +++++------
2 files changed, 152 insertions(+), 145 deletions(-)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h
index f715fb0910..91d360be62 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -411,144 +411,151 @@ struct ice_aqc_vsi_props {
#define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE BIT(7)
u8 sw_flags2;
#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S 0
-#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M \
- (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
+#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M (0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)
#define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA BIT(0)
#define ICE_AQ_VSI_SW_FLAG_LAN_ENA BIT(4)
u8 veb_stat_id;
#define ICE_AQ_VSI_SW_VEB_STAT_ID_S 0
-#define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)
+#define ICE_AQ_VSI_SW_VEB_STAT_ID_M (0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)
#define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID BIT(5)
/* security section */
u8 sec_flags;
#define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD BIT(0)
#define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF BIT(2)
-#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4
-#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)
+#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S 4
+#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M (0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)
#define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA BIT(0)
u8 sec_reserved;
/* VLAN section */
- __le16 pvid; /* VLANS include priority bits */
- u8 pvlan_reserved[2];
- u8 vlan_flags;
-#define ICE_AQ_VSI_VLAN_MODE_S 0
-#define ICE_AQ_VSI_VLAN_MODE_M (0x3 << ICE_AQ_VSI_VLAN_MODE_S)
-#define ICE_AQ_VSI_VLAN_MODE_UNTAGGED 0x1
-#define ICE_AQ_VSI_VLAN_MODE_TAGGED 0x2
-#define ICE_AQ_VSI_VLAN_MODE_ALL 0x3
-#define ICE_AQ_VSI_PVLAN_INSERT_PVID BIT(2)
-#define ICE_AQ_VSI_VLAN_EMOD_S 3
-#define ICE_AQ_VSI_VLAN_EMOD_M (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
-#define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH (0x0 << ICE_AQ_VSI_VLAN_EMOD_S)
-#define ICE_AQ_VSI_VLAN_EMOD_STR_UP (0x1 << ICE_AQ_VSI_VLAN_EMOD_S)
-#define ICE_AQ_VSI_VLAN_EMOD_STR (0x2 << ICE_AQ_VSI_VLAN_EMOD_S)
-#define ICE_AQ_VSI_VLAN_EMOD_NOTHING (0x3 << ICE_AQ_VSI_VLAN_EMOD_S)
- u8 pvlan_reserved2[3];
+ __le16 port_based_inner_vlan; /* VLANS include priority bits */
+ u8 inner_vlan_reserved[2];
+ u8 inner_vlan_flags;
+#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S 0
+#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S)
+#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1
+#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED 0x2
+#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL 0x3
+#define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID BIT(2)
+#define ICE_AQ_VSI_INNER_VLAN_EMODE_S 3
+#define ICE_AQ_VSI_INNER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
+#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH (0x0 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
+#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP (0x1 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
+#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR (0x2 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
+#define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING (0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)
+#define ICE_AQ_VSI_INNER_VLAN_BLOCK_TX_DESC BIT(5)
+ u8 inner_vlan_reserved2[3];
/* ingress egress up sections */
__le32 ingress_table; /* bitmap, 3 bits per up */
-#define ICE_AQ_VSI_UP_TABLE_UP0_S 0
-#define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)
-#define ICE_AQ_VSI_UP_TABLE_UP1_S 3
-#define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)
-#define ICE_AQ_VSI_UP_TABLE_UP2_S 6
-#define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)
-#define ICE_AQ_VSI_UP_TABLE_UP3_S 9
-#define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)
-#define ICE_AQ_VSI_UP_TABLE_UP4_S 12
-#define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)
-#define ICE_AQ_VSI_UP_TABLE_UP5_S 15
-#define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)
-#define ICE_AQ_VSI_UP_TABLE_UP6_S 18
-#define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)
-#define ICE_AQ_VSI_UP_TABLE_UP7_S 21
-#define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)
+#define ICE_AQ_VSI_UP_TABLE_UP0_S 0
+#define ICE_AQ_VSI_UP_TABLE_UP0_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)
+#define ICE_AQ_VSI_UP_TABLE_UP1_S 3
+#define ICE_AQ_VSI_UP_TABLE_UP1_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)
+#define ICE_AQ_VSI_UP_TABLE_UP2_S 6
+#define ICE_AQ_VSI_UP_TABLE_UP2_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)
+#define ICE_AQ_VSI_UP_TABLE_UP3_S 9
+#define ICE_AQ_VSI_UP_TABLE_UP3_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)
+#define ICE_AQ_VSI_UP_TABLE_UP4_S 12
+#define ICE_AQ_VSI_UP_TABLE_UP4_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)
+#define ICE_AQ_VSI_UP_TABLE_UP5_S 15
+#define ICE_AQ_VSI_UP_TABLE_UP5_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)
+#define ICE_AQ_VSI_UP_TABLE_UP6_S 18
+#define ICE_AQ_VSI_UP_TABLE_UP6_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)
+#define ICE_AQ_VSI_UP_TABLE_UP7_S 21
+#define ICE_AQ_VSI_UP_TABLE_UP7_M (0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)
__le32 egress_table; /* same defines as for ingress table */
/* outer tags section */
- __le16 outer_tag;
- u8 outer_tag_flags;
-#define ICE_AQ_VSI_OUTER_TAG_MODE_S 0
-#define ICE_AQ_VSI_OUTER_TAG_MODE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S)
-#define ICE_AQ_VSI_OUTER_TAG_NOTHING 0x0
-#define ICE_AQ_VSI_OUTER_TAG_REMOVE 0x1
-#define ICE_AQ_VSI_OUTER_TAG_COPY 0x2
-#define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2
-#define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)
-#define ICE_AQ_VSI_OUTER_TAG_NONE 0x0
-#define ICE_AQ_VSI_OUTER_TAG_STAG 0x1
-#define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2
-#define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3
-#define ICE_AQ_VSI_OUTER_TAG_INSERT BIT(4)
-#define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6)
- u8 outer_tag_reserved;
+ __le16 port_based_outer_vlan;
+ u8 outer_vlan_flags;
+#define ICE_AQ_VSI_OUTER_VLAN_EMODE_S 0
+#define ICE_AQ_VSI_OUTER_VLAN_EMODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S)
+#define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH 0x0
+#define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP 0x1
+#define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW 0x2
+#define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING 0x3
+#define ICE_AQ_VSI_OUTER_TAG_TYPE_S 2
+#define ICE_AQ_VSI_OUTER_TAG_TYPE_M (0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)
+#define ICE_AQ_VSI_OUTER_TAG_NONE 0x0
+#define ICE_AQ_VSI_OUTER_TAG_STAG 0x1
+#define ICE_AQ_VSI_OUTER_TAG_VLAN_8100 0x2
+#define ICE_AQ_VSI_OUTER_TAG_VLAN_9100 0x3
+#define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT BIT(4)
+#define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST BIT(4)
+#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S 5
+#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M (0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S)
+#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED 0x1
+#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED 0x2
+#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL 0x3
+#define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC BIT(7)
+ u8 outer_vlan_reserved;
/* queue mapping section */
__le16 mapping_flags;
-#define ICE_AQ_VSI_Q_MAP_CONTIG 0x0
-#define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0)
+#define ICE_AQ_VSI_Q_MAP_CONTIG 0x0
+#define ICE_AQ_VSI_Q_MAP_NONCONTIG BIT(0)
__le16 q_mapping[16];
-#define ICE_AQ_VSI_Q_S 0
-#define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S)
+#define ICE_AQ_VSI_Q_S 0
+#define ICE_AQ_VSI_Q_M (0x7FF << ICE_AQ_VSI_Q_S)
__le16 tc_mapping[8];
-#define ICE_AQ_VSI_TC_Q_OFFSET_S 0
-#define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)
-#define ICE_AQ_VSI_TC_Q_NUM_S 11
-#define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S)
+#define ICE_AQ_VSI_TC_Q_OFFSET_S 0
+#define ICE_AQ_VSI_TC_Q_OFFSET_M (0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)
+#define ICE_AQ_VSI_TC_Q_NUM_S 11
+#define ICE_AQ_VSI_TC_Q_NUM_M (0xF << ICE_AQ_VSI_TC_Q_NUM_S)
/* queueing option section */
u8 q_opt_rss;
-#define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0
-#define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)
-#define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0
-#define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2
-#define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3
-#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2
-#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)
-#define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6
-#define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
-#define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
-#define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
-#define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
-#define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
+#define ICE_AQ_VSI_Q_OPT_RSS_LUT_S 0
+#define ICE_AQ_VSI_Q_OPT_RSS_LUT_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)
+#define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI 0x0
+#define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF 0x2
+#define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL 0x3
+#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S 2
+#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M (0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)
+#define ICE_AQ_VSI_Q_OPT_RSS_HASH_S 6
+#define ICE_AQ_VSI_Q_OPT_RSS_HASH_M (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
+#define ICE_AQ_VSI_Q_OPT_RSS_TPLZ (0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
+#define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ (0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
+#define ICE_AQ_VSI_Q_OPT_RSS_XOR (0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
+#define ICE_AQ_VSI_Q_OPT_RSS_JHASH (0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)
u8 q_opt_tc;
-#define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0
-#define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)
-#define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7)
+#define ICE_AQ_VSI_Q_OPT_TC_OVR_S 0
+#define ICE_AQ_VSI_Q_OPT_TC_OVR_M (0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)
+#define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR BIT(7)
u8 q_opt_flags;
-#define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0)
+#define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN BIT(0)
u8 q_opt_reserved[3];
/* outer up section */
__le32 outer_up_table; /* same structure and defines as ingress tbl */
/* ACL section */
__le16 acl_def_act;
-#define ICE_AQ_VSI_ACL_DEF_RX_PROF_S 0
-#define ICE_AQ_VSI_ACL_DEF_RX_PROF_M (0xF << ICE_AQ_VSI_ACL_DEF_RX_PROF_S)
-#define ICE_AQ_VSI_ACL_DEF_RX_TABLE_S 4
-#define ICE_AQ_VSI_ACL_DEF_RX_TABLE_M (0xF << ICE_AQ_VSI_ACL_DEF_RX_TABLE_S)
-#define ICE_AQ_VSI_ACL_DEF_TX_PROF_S 8
-#define ICE_AQ_VSI_ACL_DEF_TX_PROF_M (0xF << ICE_AQ_VSI_ACL_DEF_TX_PROF_S)
-#define ICE_AQ_VSI_ACL_DEF_TX_TABLE_S 12
-#define ICE_AQ_VSI_ACL_DEF_TX_TABLE_M (0xF << ICE_AQ_VSI_ACL_DEF_TX_TABLE_S)
+#define ICE_AQ_VSI_ACL_DEF_RX_PROF_S 0
+#define ICE_AQ_VSI_ACL_DEF_RX_PROF_M (0xF << ICE_AQ_VSI_ACL_DEF_RX_PROF_S)
+#define ICE_AQ_VSI_ACL_DEF_RX_TABLE_S 4
+#define ICE_AQ_VSI_ACL_DEF_RX_TABLE_M (0xF << ICE_AQ_VSI_ACL_DEF_RX_TABLE_S)
+#define ICE_AQ_VSI_ACL_DEF_TX_PROF_S 8
+#define ICE_AQ_VSI_ACL_DEF_TX_PROF_M (0xF << ICE_AQ_VSI_ACL_DEF_TX_PROF_S)
+#define ICE_AQ_VSI_ACL_DEF_TX_TABLE_S 12
+#define ICE_AQ_VSI_ACL_DEF_TX_TABLE_M (0xF << ICE_AQ_VSI_ACL_DEF_TX_TABLE_S)
/* flow director section */
__le16 fd_options;
-#define ICE_AQ_VSI_FD_ENABLE BIT(0)
-#define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1)
-#define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3)
+#define ICE_AQ_VSI_FD_ENABLE BIT(0)
+#define ICE_AQ_VSI_FD_TX_AUTO_ENABLE BIT(1)
+#define ICE_AQ_VSI_FD_PROG_ENABLE BIT(3)
__le16 max_fd_fltr_dedicated;
__le16 max_fd_fltr_shared;
__le16 fd_def_q;
-#define ICE_AQ_VSI_FD_DEF_Q_S 0
-#define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)
-#define ICE_AQ_VSI_FD_DEF_GRP_S 12
-#define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)
+#define ICE_AQ_VSI_FD_DEF_Q_S 0
+#define ICE_AQ_VSI_FD_DEF_Q_M (0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)
+#define ICE_AQ_VSI_FD_DEF_GRP_S 12
+#define ICE_AQ_VSI_FD_DEF_GRP_M (0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)
__le16 fd_report_opt;
-#define ICE_AQ_VSI_FD_REPORT_Q_S 0
-#define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)
-#define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12
-#define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)
-#define ICE_AQ_VSI_FD_DEF_DROP BIT(15)
+#define ICE_AQ_VSI_FD_REPORT_Q_S 0
+#define ICE_AQ_VSI_FD_REPORT_Q_M (0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)
+#define ICE_AQ_VSI_FD_DEF_PRIORITY_S 12
+#define ICE_AQ_VSI_FD_DEF_PRIORITY_M (0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)
+#define ICE_AQ_VSI_FD_DEF_DROP BIT(15)
/* PASID section */
__le32 pasid_id;
-#define ICE_AQ_VSI_PASID_ID_S 0
-#define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S)
-#define ICE_AQ_VSI_PASID_ID_VALID BIT(31)
+#define ICE_AQ_VSI_PASID_ID_S 0
+#define ICE_AQ_VSI_PASID_ID_M (0xFFFFF << ICE_AQ_VSI_PASID_ID_S)
+#define ICE_AQ_VSI_PASID_ID_VALID BIT(31)
u8 reserved[24];
};
diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c
index f30199fc23..7f78cd36cd 100644
--- a/drivers/net/ice/ice_ethdev.c
+++ b/drivers/net/ice/ice_ethdev.c
@@ -1131,28 +1131,28 @@ ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
if (vsi->info.valid_sections &
rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
if (on) {
- if ((vsi->info.outer_tag_flags &
- ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
- ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
+ if ((vsi->info.outer_vlan_flags &
+ ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST) ==
+ ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST)
return 0; /* already on */
} else {
- if (!(vsi->info.outer_tag_flags &
- ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
+ if (!(vsi->info.outer_vlan_flags &
+ ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST))
return 0; /* already off */
}
}
if (on)
- qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
+ qinq_flags = ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST;
else
qinq_flags = 0;
/* clear global insertion and use per packet insertion */
- vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
- vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
- vsi->info.outer_tag_flags |= qinq_flags;
+ vsi->info.outer_vlan_flags &= ~(ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT);
+ vsi->info.outer_vlan_flags &= ~(ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST);
+ vsi->info.outer_vlan_flags |= qinq_flags;
/* use default vlan type 0x8100 */
- vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
- vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
+ vsi->info.outer_vlan_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
+ vsi->info.outer_vlan_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
ICE_AQ_VSI_OUTER_TAG_TYPE_S;
(void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
ctxt.info.valid_sections =
@@ -1184,27 +1184,27 @@ ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
if (vsi->info.valid_sections &
rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
if (on) {
- if ((vsi->info.outer_tag_flags &
- ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
- ICE_AQ_VSI_OUTER_TAG_COPY)
+ if ((vsi->info.outer_vlan_flags &
+ ICE_AQ_VSI_OUTER_VLAN_EMODE_M) ==
+ ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW)
return 0; /* already on */
} else {
- if ((vsi->info.outer_tag_flags &
- ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
- ICE_AQ_VSI_OUTER_TAG_NOTHING)
+ if ((vsi->info.outer_vlan_flags &
+ ICE_AQ_VSI_OUTER_VLAN_EMODE_M) ==
+ ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH)
return 0; /* already off */
}
}
if (on)
- qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
+ qinq_flags = ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW;
else
- qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
- vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
- vsi->info.outer_tag_flags |= qinq_flags;
+ qinq_flags = ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH;
+ vsi->info.outer_vlan_flags &= ~(ICE_AQ_VSI_OUTER_VLAN_EMODE_M);
+ vsi->info.outer_vlan_flags |= qinq_flags;
/* use default vlan type 0x8100 */
- vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
- vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
+ vsi->info.outer_vlan_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
+ vsi->info.outer_vlan_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
ICE_AQ_VSI_OUTER_TAG_TYPE_S;
(void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
ctxt.info.valid_sections =
@@ -1582,8 +1582,8 @@ ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
vsi_ctx.info.sw_id = hw->port_info->sw_id;
vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
/* Allow all untagged or tagged packets */
- vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
- vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
+ vsi_ctx.info.inner_vlan_flags = ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
+ vsi_ctx.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
@@ -4101,24 +4101,24 @@ ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
if (vsi->info.valid_sections &
rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
if (on) {
- if ((vsi->info.vlan_flags &
- ICE_AQ_VSI_VLAN_EMOD_M) ==
- ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
+ if ((vsi->info.inner_vlan_flags &
+ ICE_AQ_VSI_INNER_VLAN_EMODE_M) ==
+ ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH)
return 0; /* already on */
} else {
- if ((vsi->info.vlan_flags &
- ICE_AQ_VSI_VLAN_EMOD_M) ==
- ICE_AQ_VSI_VLAN_EMOD_NOTHING)
+ if ((vsi->info.inner_vlan_flags &
+ ICE_AQ_VSI_INNER_VLAN_EMODE_M) ==
+ ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING)
return 0; /* already off */
}
}
if (on)
- vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
+ vlan_flags = ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH;
else
- vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
- vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
- vsi->info.vlan_flags |= vlan_flags;
+ vlan_flags = ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
+ vsi->info.inner_vlan_flags &= ~(ICE_AQ_VSI_INNER_VLAN_EMODE_M);
+ vsi->info.inner_vlan_flags |= vlan_flags;
(void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
ctxt.info.valid_sections =
rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
@@ -4602,24 +4602,24 @@ ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
}
if (info->on) {
- vsi->info.pvid = info->config.pvid;
+ vsi->info.port_based_inner_vlan = info->config.pvid;
/**
* If insert pvid is enabled, only tagged pkts are
* allowed to be sent out.
*/
- vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
- ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
+ vlan_flags = ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
+ ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
} else {
- vsi->info.pvid = 0;
+ vsi->info.port_based_inner_vlan = 0;
if (info->config.reject.tagged == 0)
- vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
+ vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED;
if (info->config.reject.untagged == 0)
- vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
+ vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
}
- vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
- ICE_AQ_VSI_VLAN_MODE_M);
- vsi->info.vlan_flags |= vlan_flags;
+ vsi->info.inner_vlan_flags &= ~(ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
+ ICE_AQ_VSI_INNER_VLAN_EMODE_M);
+ vsi->info.inner_vlan_flags |= vlan_flags;
memset(&ctxt, 0, sizeof(ctxt));
rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
ctxt.info.valid_sections =
--
2.32.0
next prev parent reply other threads:[~2021-06-11 7:37 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-11 6:58 [PATCH 20.11 v1 00/18] Backport the new VLAN design for Intel ice PMD Haiyue Wang
2021-06-11 6:58 ` [dpdk-stable] [PATCH 20.11 v1 01/18] net/ice/base: align add VSI and update VSI AQ command buffer Haiyue Wang
2021-06-11 6:58 ` [dpdk-stable] [PATCH 20.11 v1 02/18] net/ice/base: add interface to support configuring VLAN mode Haiyue Wang
2021-06-11 6:58 ` [dpdk-stable] [PATCH 20.11 v1 03/18] net/ice/base: fix outer VLAN related macro Haiyue Wang
2021-06-11 6:58 ` [dpdk-stable] [PATCH 20.11 v1 04/18] net/ice/base: add VLAN TPID for VLAN filters Haiyue Wang
2021-06-11 6:58 ` [dpdk-stable] [PATCH 20.11 v1 05/18] net/ice/base: support checking double VLAN mode Haiyue Wang
2021-06-11 6:58 ` [dpdk-stable] [PATCH 20.11 v1 06/18] net/ice/base: support configuring device in " Haiyue Wang
2021-06-11 6:58 ` [dpdk-stable] [PATCH 20.11 v1 07/18] net/ice/base: do not set VLAN mode in DCF mode Haiyue Wang
2021-06-11 6:58 ` [dpdk-stable] [PATCH 20.11 v1 08/18] net/ice/base: update boost TCAM for DVM Haiyue Wang
2021-06-11 6:58 ` [dpdk-stable] [PATCH 20.11 v1 09/18] net/ice/base: change protocol ID for VLAN in DVM Haiyue Wang
2021-06-11 6:58 ` [dpdk-stable] [PATCH 20.11 v1 10/18] net/ice/base: refactor post DDP download VLAN mode config Haiyue Wang
2021-06-11 6:58 ` [dpdk-stable] [PATCH 20.11 v1 11/18] net/ice/base: log if DDP/FW do not support QinQ Haiyue Wang
2021-06-11 6:58 ` [dpdk-stable] [PATCH 20.11 v1 12/18] net/ice/base: add ethertype offset for QinQ dummy packet Haiyue Wang
2021-06-11 6:58 ` [PATCH 20.11 v1 13/18] net/ice/base: add inner VLAN protocol type for QinQ filter Haiyue Wang
2021-06-11 6:58 ` [dpdk-stable] [PATCH 20.11 v1 14/18] net/ice/base: fix QinQ PPPoE dummy packet selection Haiyue Wang
2021-06-11 6:58 ` [dpdk-stable] [PATCH 20.11 v1 15/18] net/ice: fix VLAN strip for double VLAN Haiyue Wang
2021-06-11 6:58 ` [dpdk-stable] [PATCH 20.11 v1 16/18] net/ice: fix VLAN 0 adding based on VLAN mode Haiyue Wang
2021-06-11 6:58 ` [dpdk-stable] [PATCH 20.11 v1 17/18] net/ice: enable QinQ filter for switch Haiyue Wang
2021-06-11 6:58 ` [dpdk-stable] [PATCH 20.11 v1 18/18] net/ice: update QinQ switch filter handling Haiyue Wang
2021-06-11 7:15 ` [dpdk-stable] [PATCH 20.11 v2 00/18] Backport the new VLAN design for Intel ice PMD Haiyue Wang
2021-06-11 7:15 ` Haiyue Wang [this message]
2021-06-11 7:15 ` [dpdk-stable] [PATCH 20.11 v2 02/18] net/ice/base: add interface to support configuring VLAN mode Haiyue Wang
2021-06-11 7:15 ` [dpdk-stable] [PATCH 20.11 v2 03/18] net/ice/base: fix outer VLAN related macro Haiyue Wang
2021-06-11 7:15 ` [dpdk-stable] [PATCH 20.11 v2 04/18] net/ice/base: add VLAN TPID for VLAN filters Haiyue Wang
2021-06-11 7:15 ` [dpdk-stable] [PATCH 20.11 v2 05/18] net/ice/base: support checking double VLAN mode Haiyue Wang
2021-06-11 7:15 ` [dpdk-stable] [PATCH 20.11 v2 06/18] net/ice/base: support configuring device in " Haiyue Wang
2021-06-11 7:15 ` [dpdk-stable] [PATCH 20.11 v2 07/18] net/ice/base: do not set VLAN mode in DCF mode Haiyue Wang
2021-06-11 7:15 ` [dpdk-stable] [PATCH 20.11 v2 08/18] net/ice/base: update boost TCAM for DVM Haiyue Wang
2021-06-11 7:15 ` [dpdk-stable] [PATCH 20.11 v2 09/18] net/ice/base: change protocol ID for VLAN in DVM Haiyue Wang
2021-06-11 7:15 ` [dpdk-stable] [PATCH 20.11 v2 10/18] net/ice/base: refactor post DDP download VLAN mode config Haiyue Wang
2021-06-11 7:15 ` [dpdk-stable] [PATCH 20.11 v2 11/18] net/ice/base: log if DDP/FW do not support QinQ Haiyue Wang
2021-06-11 7:15 ` [dpdk-stable] [PATCH 20.11 v2 12/18] net/ice/base: add ethertype offset for QinQ dummy packet Haiyue Wang
2021-06-11 7:15 ` [dpdk-stable] [PATCH 20.11 v2 13/18] net/ice/base: add inner VLAN protocol type for QinQ filter Haiyue Wang
2021-06-11 7:15 ` [dpdk-stable] [PATCH 20.11 v2 14/18] net/ice/base: fix QinQ PPPoE dummy packet selection Haiyue Wang
2021-06-11 7:15 ` [dpdk-stable] [PATCH 20.11 v2 15/18] net/ice: fix VLAN strip for double VLAN Haiyue Wang
2021-06-11 7:15 ` [dpdk-stable] [PATCH 20.11 v2 16/18] net/ice: fix VLAN 0 adding based on VLAN mode Haiyue Wang
2021-06-11 7:15 ` [dpdk-stable] [PATCH 20.11 v2 17/18] net/ice: enable QinQ filter for switch Haiyue Wang
2021-06-11 7:15 ` [dpdk-stable] [PATCH 20.11 v2 18/18] net/ice: update QinQ switch filter handling Haiyue Wang
2021-06-16 15:47 ` [dpdk-stable] [PATCH 20.11 v2 00/18] Backport the new VLAN design for Intel ice PMD Luca Boccassi
2021-06-17 1:16 ` Wang, Haiyue
2021-06-17 8:53 ` Xueming(Steven) Li
2021-06-17 10:04 ` Kevin Traynor
2021-06-18 3:22 ` Wang, Haiyue
2021-06-18 10:12 ` Kevin Traynor
2021-06-18 11:46 ` Wang, Haiyue
2021-06-21 8:28 ` Thomas Monjalon
2021-06-21 8:34 ` Wang, Haiyue
2021-06-21 8:59 ` Kevin Traynor
2021-06-21 10:28 ` Kevin Traynor
2021-06-22 1:41 ` Wang, Haiyue
2021-06-18 1:56 ` Wang, Haiyue
2021-06-20 13:47 ` Xueming(Steven) Li
2021-06-21 1:35 ` Wang, Haiyue
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