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intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT043.mail.protection.outlook.com (10.13.174.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4219.21 via Frontend Transport; Fri, 11 Jun 2021 23:13:12 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 11 Jun 2021 23:13:10 +0000 From: Xueming Li To: Adam Dybkowski CC: Luca Boccassi , Fan Zhang , dpdk stable Date: Sat, 12 Jun 2021 07:03:04 +0800 Message-ID: <20210611230433.8208-90-xuemingl@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210611230433.8208-1-xuemingl@nvidia.com> References: <20210510160258.30982-229-xuemingl@nvidia.com> <20210611230433.8208-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a8d8feb0-577a-4986-886f-08d92d2e7c37 X-MS-TrafficTypeDiagnostic: CH0PR12MB5347: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4714; 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SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(396003)(346002)(136003)(376002)(39860400002)(36840700001)(46966006)(70586007)(478600001)(82310400003)(6916009)(26005)(36756003)(8676002)(82740400003)(966005)(55016002)(6286002)(8936002)(86362001)(356005)(47076005)(53546011)(186003)(16526019)(7696005)(4326008)(54906003)(36860700001)(83380400001)(5660300002)(1076003)(336012)(316002)(36906005)(6666004)(7636003)(426003)(2906002)(70206006)(2616005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jun 2021 23:13:12.3816 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a8d8feb0-577a-4986-886f-08d92d2e7c37 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT043.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5347 Subject: [dpdk-stable] patch 'compress/qat: enable compression on GEN3' has been queued to stable release 20.11.2 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Hi, FYI, your patch has been queued to stable release 20.11.2 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 06/14/21. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/steevenlee/dpdk This queued commit can be viewed at: https://github.com/steevenlee/dpdk/commit/afe3a7f202aea54ace3772f0f414fa539eee5a2b Thanks. Xueming Li --- >From afe3a7f202aea54ace3772f0f414fa539eee5a2b Mon Sep 17 00:00:00 2001 From: Adam Dybkowski Date: Wed, 28 Apr 2021 15:41:42 +0100 Subject: [PATCH] compress/qat: enable compression on GEN3 Cc: Luca Boccassi [ upstream commit da573c0e4205d818cd602eaa27c720896f3b6f1c ] This patch enables the compression on QAT GEN3 (on hardware versions that support it) and changes the error message shown on older hardware versions that don't support the compression. It also fixes the crash that happened on IM buffer allocation failure (not enough memory) during the PMD cleaning phase. Fixes: a124830a6f00 ("compress/qat: enable dynamic huffman encoding") Fixes: 352332744c3a ("compress/qat: add dynamic SGL allocation") Signed-off-by: Adam Dybkowski Acked-by: Fan Zhang --- drivers/compress/qat/qat_comp.c | 7 +- drivers/compress/qat/qat_comp_pmd.c | 111 +++++++++++++++++++--------- 2 files changed, 79 insertions(+), 39 deletions(-) diff --git a/drivers/compress/qat/qat_comp.c b/drivers/compress/qat/qat_comp.c index 3a064ec3b2..7ac25a3b4c 100644 --- a/drivers/compress/qat/qat_comp.c +++ b/drivers/compress/qat/qat_comp.c @@ -191,8 +191,8 @@ qat_comp_build_request(void *in_op, uint8_t *out_msg, ICP_QAT_FW_COMP_EOP : ICP_QAT_FW_COMP_NOT_EOP, ICP_QAT_FW_COMP_NOT_BFINAL, - ICP_QAT_FW_COMP_NO_CNV, - ICP_QAT_FW_COMP_NO_CNV_RECOVERY); + ICP_QAT_FW_COMP_CNV, + ICP_QAT_FW_COMP_CNV_RECOVERY); } /* common for sgl and flat buffers */ @@ -603,7 +603,8 @@ qat_comp_process_response(void **op, uint8_t *resp, void *op_cookie, rx_op->status = RTE_COMP_OP_STATUS_ERROR; rx_op->debug_status = ERR_CODE_QAT_COMP_WRONG_FW; *op = (void *)rx_op; - QAT_DP_LOG(ERR, "QAT has wrong firmware"); + QAT_DP_LOG(ERR, + "This QAT hardware doesn't support compression operation"); ++(*dequeue_err_count); return 1; } diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c index 18ecb34ba7..8de41f6b6e 100644 --- a/drivers/compress/qat/qat_comp_pmd.c +++ b/drivers/compress/qat/qat_comp_pmd.c @@ -82,13 +82,13 @@ qat_comp_qp_release(struct rte_compressdev *dev, uint16_t queue_pair_id) qat_private->qat_dev->qps_in_use[QAT_SERVICE_COMPRESSION][queue_pair_id] = NULL; - for (i = 0; i < qp->nb_descriptors; i++) { - - struct qat_comp_op_cookie *cookie = qp->op_cookies[i]; + if (qp != NULL) + for (i = 0; i < qp->nb_descriptors; i++) { + struct qat_comp_op_cookie *cookie = qp->op_cookies[i]; - rte_free(cookie->qat_sgl_src_d); - rte_free(cookie->qat_sgl_dst_d); - } + rte_free(cookie->qat_sgl_src_d); + rte_free(cookie->qat_sgl_dst_d); + } return qat_qp_release((struct qat_qp **) &(dev->data->queue_pairs[queue_pair_id])); @@ -198,7 +198,7 @@ qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev, struct array_of_ptrs *array_of_pointers; int size_of_ptr_array; uint32_t full_size; - uint32_t offset_of_sgls, offset_of_flat_buffs = 0; + uint32_t offset_of_flat_buffs; int i; int num_im_sgls = qat_gen_config[ comp_dev->qat_dev->qat_dev_gen].comp_num_im_bufs_required; @@ -213,31 +213,31 @@ qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev, return memzone; } - /* Create a memzone to hold intermediate buffers and associated - * meta-data needed by the firmware. The memzone contains 3 parts: + /* Create multiple memzones to hold intermediate buffers and associated + * meta-data needed by the firmware. + * The first memzone contains: * - a list of num_im_sgls physical pointers to sgls - * - the num_im_sgl sgl structures, each pointing to - * QAT_NUM_BUFS_IN_IM_SGL flat buffers - * - the flat buffers: num_im_sgl * QAT_NUM_BUFS_IN_IM_SGL - * buffers, each of buff_size + * All other memzones contain: + * - the sgl structure, pointing to QAT_NUM_BUFS_IN_IM_SGL flat buffers + * - the flat buffers: QAT_NUM_BUFS_IN_IM_SGL buffers, + * each of buff_size * num_im_sgls depends on the hardware generation of the device * buff_size comes from the user via the config file */ size_of_ptr_array = num_im_sgls * sizeof(phys_addr_t); - offset_of_sgls = (size_of_ptr_array + (~QAT_64_BYTE_ALIGN_MASK)) - & QAT_64_BYTE_ALIGN_MASK; - offset_of_flat_buffs = - offset_of_sgls + num_im_sgls * sizeof(struct qat_inter_sgl); + offset_of_flat_buffs = sizeof(struct qat_inter_sgl); full_size = offset_of_flat_buffs + - num_im_sgls * buff_size * QAT_NUM_BUFS_IN_IM_SGL; + buff_size * QAT_NUM_BUFS_IN_IM_SGL; - memzone = rte_memzone_reserve_aligned(inter_buff_mz_name, full_size, + memzone = rte_memzone_reserve_aligned(inter_buff_mz_name, + size_of_ptr_array, comp_dev->compressdev->data->socket_id, RTE_MEMZONE_IOVA_CONTIG, QAT_64_BYTE_ALIGN); if (memzone == NULL) { - QAT_LOG(ERR, "Can't allocate intermediate buffers" - " for device %s", comp_dev->qat_dev->name); + QAT_LOG(ERR, + "Can't allocate intermediate buffers for device %s", + comp_dev->qat_dev->name); return NULL; } @@ -246,17 +246,50 @@ qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev, QAT_LOG(DEBUG, "Memzone %s: addr = %p, phys = 0x%"PRIx64 ", size required %d, size created %zu", inter_buff_mz_name, mz_start, mz_start_phys, - full_size, memzone->len); + size_of_ptr_array, memzone->len); array_of_pointers = (struct array_of_ptrs *)mz_start; for (i = 0; i < num_im_sgls; i++) { - uint32_t curr_sgl_offset = - offset_of_sgls + i * sizeof(struct qat_inter_sgl); - struct qat_inter_sgl *sgl = - (struct qat_inter_sgl *)(mz_start + curr_sgl_offset); + const struct rte_memzone *mz; + struct qat_inter_sgl *sgl; int lb; - array_of_pointers->pointer[i] = mz_start_phys + curr_sgl_offset; + snprintf(inter_buff_mz_name, RTE_MEMZONE_NAMESIZE, + "%s_inter_buff_%d", comp_dev->qat_dev->name, i); + mz = rte_memzone_lookup(inter_buff_mz_name); + if (mz == NULL) { + mz = rte_memzone_reserve_aligned(inter_buff_mz_name, + full_size, + comp_dev->compressdev->data->socket_id, + RTE_MEMZONE_IOVA_CONTIG, + QAT_64_BYTE_ALIGN); + if (mz == NULL) { + QAT_LOG(ERR, + "Can't allocate intermediate buffers for device %s", + comp_dev->qat_dev->name); + while (--i >= 0) { + snprintf(inter_buff_mz_name, + RTE_MEMZONE_NAMESIZE, + "%s_inter_buff_%d", + comp_dev->qat_dev->name, + i); + rte_memzone_free( + rte_memzone_lookup( + inter_buff_mz_name)); + } + rte_memzone_free(memzone); + return NULL; + } + } + + QAT_LOG(DEBUG, "Memzone %s: addr = %p, phys = 0x%"PRIx64 + ", size required %d, size created %zu", + inter_buff_mz_name, mz->addr, mz->iova, + full_size, mz->len); + + array_of_pointers->pointer[i] = mz->iova; + + sgl = (struct qat_inter_sgl *) mz->addr; sgl->num_bufs = QAT_NUM_BUFS_IN_IM_SGL; sgl->num_mapped_bufs = 0; sgl->resrvd = 0; @@ -268,8 +301,8 @@ qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev, #endif for (lb = 0; lb < QAT_NUM_BUFS_IN_IM_SGL; lb++) { sgl->buffers[lb].addr = - mz_start_phys + offset_of_flat_buffs + - (((i * QAT_NUM_BUFS_IN_IM_SGL) + lb) * buff_size); + mz->iova + offset_of_flat_buffs + + lb * buff_size; sgl->buffers[lb].len = buff_size; sgl->buffers[lb].resrvd = 0; #if QAT_IM_BUFFER_DEBUG @@ -281,7 +314,7 @@ qat_comp_setup_inter_buffers(struct qat_comp_dev_private *comp_dev, } #if QAT_IM_BUFFER_DEBUG QAT_DP_HEXDUMP_LOG(DEBUG, "IM buffer memzone start:", - mz_start, offset_of_flat_buffs + 32); + memzone->addr, size_of_ptr_array); #endif return memzone; } @@ -444,6 +477,16 @@ _qat_comp_dev_config_clear(struct qat_comp_dev_private *comp_dev) { /* Free intermediate buffers */ if (comp_dev->interm_buff_mz) { + char mz_name[RTE_MEMZONE_NAMESIZE]; + int i = qat_gen_config[ + comp_dev->qat_dev->qat_dev_gen].comp_num_im_bufs_required; + + while (--i >= 0) { + snprintf(mz_name, RTE_MEMZONE_NAMESIZE, + "%s_inter_buff_%d", + comp_dev->qat_dev->name, i); + rte_memzone_free(rte_memzone_lookup(mz_name)); + } rte_memzone_free(comp_dev->interm_buff_mz); comp_dev->interm_buff_mz = NULL; } @@ -607,7 +650,8 @@ qat_comp_pmd_dequeue_first_op_burst(void *qp, struct rte_comp_op **ops, tmp_qp->qat_dev->comp_dev->compressdev->dev_ops = &compress_qat_dummy_ops; - QAT_LOG(ERR, "QAT PMD detected wrong FW version !"); + QAT_LOG(ERR, + "This QAT hardware doesn't support compression operation"); } else { tmp_qp->qat_dev->comp_dev->compressdev->dequeue_burst = @@ -656,11 +700,6 @@ qat_comp_dev_create(struct qat_pci_device *qat_pci_dev, int i = 0; struct qat_device_info *qat_dev_instance = &qat_pci_devs[qat_pci_dev->qat_dev_id]; - if (qat_pci_dev->qat_dev_gen == QAT_GEN3) { - QAT_LOG(ERR, "Compression PMD not supported on QAT c4xxx"); - return 0; - } - struct rte_compressdev_pmd_init_params init_params = { .name = "", .socket_id = qat_dev_instance->pci_dev->device.numa_node, -- 2.25.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2021-06-12 06:53:58.923537800 +0800 +++ 0090-compress-qat-enable-compression-on-GEN3.patch 2021-06-12 06:53:56.420000000 +0800 @@ -1 +1 @@ -From da573c0e4205d818cd602eaa27c720896f3b6f1c Mon Sep 17 00:00:00 2001 +From afe3a7f202aea54ace3772f0f414fa539eee5a2b Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Luca Boccassi + +[ upstream commit da573c0e4205d818cd602eaa27c720896f3b6f1c ] @@ -15 +17,0 @@ -Cc: stable@dpdk.org