From: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
To: <stable@dpdk.org>
Cc: <christian.ehrhardt@canonical.com>, <xuemingl@nvidia.com>,
"Viacheslav Ovsiienko" <viacheslavo@mellanox.com>
Subject: [dpdk-stable] [PATCH 19.11] net/mlx5: fix last completed built descriptor
Date: Wed, 16 Jun 2021 10:06:30 +0300 [thread overview]
Message-ID: <20210616070630.12085-1-viacheslavo@nvidia.com> (raw)
From: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
[ upstream commit 0f13d919703fb555727cc4d075272a60d2f87508 ]
The routine sending packets with Multi-Packet Write method assigns
the wqe_last variable with transmit descriptor (WQE - work queue entry)
being built. If send queue is close to full state, the WQE has no data
yet (trying to put the first packet) and there is no enough space
in descriptor for the next packet the WQE is discarded and the stored
wqe_last value becomes invalid - points to the discarded WQE.
The mlx5_tx_burst_request_completion() routine might set the completion
request flags in the WQE pointed by wqe_last, it is safe, but the next
mlx5_tx_burst call uses the WQE as the first free one and request
completion flags might be overwritten and completion request will be
lost causing the transmit datapath malfunction.
Fixes: 8b581c690a54 ("net/mlx5: move Tx complete request routine")
Cc: stable@dpdk.org
Signed-off-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
---
drivers/net/mlx5/mlx5_rxtx.c | 51 ++++++++++++++++++++++--------------
1 file changed, 31 insertions(+), 20 deletions(-)
diff --git a/drivers/net/mlx5/mlx5_rxtx.c b/drivers/net/mlx5/mlx5_rxtx.c
index 73dbf68d2b..7c9a09c814 100644
--- a/drivers/net/mlx5/mlx5_rxtx.c
+++ b/drivers/net/mlx5/mlx5_rxtx.c
@@ -2210,6 +2210,7 @@ mlx5_tx_request_completion(struct mlx5_txq_data *restrict txq,
(uint16_t)(txq->wqe_ci - txq->wqe_comp) >= txq->wqe_thres)) {
volatile struct mlx5_wqe *last = loc->wqe_last;
+ MLX5_ASSERT(last);
txq->elts_comp = head;
if (MLX5_TXOFF_CONFIG(INLINE))
txq->wqe_comp = txq->wqe_ci;
@@ -3828,6 +3829,8 @@ mlx5_tx_sdone_empw(struct mlx5_txq_data *restrict txq,
* Total size of descriptor/data in bytes.
* @param slen
* Accumulated statistics, data bytes sent.
+ * @param wqem
+ * The base WQE for the eMPW/MPW descriptor.
* @param olx
* Configured Tx offloads mask. It is fully defined at
* compile time and may be used for optimization.
@@ -3841,9 +3844,10 @@ mlx5_tx_idone_empw(struct mlx5_txq_data *restrict txq,
struct mlx5_txq_local *restrict loc,
unsigned int len,
unsigned int slen,
+ struct mlx5_wqe *restrict wqem,
unsigned int olx __rte_unused)
{
- struct mlx5_wqe_dseg *dseg = &loc->wqe_last->dseg[0];
+ struct mlx5_wqe_dseg *dseg = &wqem->dseg[0];
assert(MLX5_TXOFF_CONFIG(INLINE));
#ifdef MLX5_PMD_SOFT_COUNTERS
@@ -3870,9 +3874,10 @@ mlx5_tx_idone_empw(struct mlx5_txq_data *restrict txq,
assert((len % MLX5_WSEG_SIZE) == 0);
len = len / MLX5_WSEG_SIZE + 2;
}
- loc->wqe_last->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | len);
+ wqem->cseg.sq_ds = rte_cpu_to_be_32(txq->qp_num_8s | len);
txq->wqe_ci += (len + 3) / 4;
loc->wqe_free -= (len + 3) / 4;
+ loc->wqe_last = wqem;
}
/**
@@ -4109,7 +4114,7 @@ mlx5_tx_burst_empw_inline(struct mlx5_txq_data *restrict txq,
pkts_n -= loc->pkts_sent;
for (;;) {
struct mlx5_wqe_dseg *restrict dseg;
- struct mlx5_wqe_eseg *restrict eseg;
+ struct mlx5_wqe *restrict wqem;
enum mlx5_txcmp_code ret;
unsigned int room, part, nlim;
unsigned int slen = 0;
@@ -4128,22 +4133,21 @@ mlx5_tx_burst_empw_inline(struct mlx5_txq_data *restrict txq,
return MLX5_TXCMP_CODE_EXIT;
if (likely(pkts_n > 1))
rte_prefetch0(*pkts);
- loc->wqe_last = txq->wqes + (txq->wqe_ci & txq->wqe_m);
+ wqem = txq->wqes + (txq->wqe_ci & txq->wqe_m);
/*
* Build eMPW title WQEBB:
* - Control Segment, eMPW opcode, zero DS
* - Ethernet Segment, no inline
*/
- mlx5_tx_cseg_init(txq, loc, loc->wqe_last, 0,
+ mlx5_tx_cseg_init(txq, loc, wqem, 0,
MLX5_OPCODE_ENHANCED_MPSW, olx);
- mlx5_tx_eseg_none(txq, loc, loc->wqe_last,
+ mlx5_tx_eseg_none(txq, loc, wqem,
olx & ~MLX5_TXOFF_CONFIG_VLAN);
- eseg = &loc->wqe_last->eseg;
- dseg = &loc->wqe_last->dseg[0];
+ dseg = &wqem->dseg[0];
/* Store the packet length for legacy MPW. */
if (MLX5_TXOFF_CONFIG(MPW))
- eseg->mss = rte_cpu_to_be_16
- (rte_pktmbuf_data_len(loc->mbuf));
+ wqem->eseg.mss = rte_cpu_to_be_16
+ (rte_pktmbuf_data_len(loc->mbuf));
room = RTE_MIN(MLX5_WQE_SIZE_MAX / MLX5_WQE_SIZE,
loc->wqe_free) * MLX5_WQE_SIZE -
MLX5_WQE_CSEG_SIZE -
@@ -4180,7 +4184,8 @@ mlx5_tx_burst_empw_inline(struct mlx5_txq_data *restrict txq,
* We have some successfully built
* packet Data Segments to send.
*/
- mlx5_tx_idone_empw(txq, loc, part, slen, olx);
+ mlx5_tx_idone_empw(txq, loc, part,
+ slen, wqem, olx);
return MLX5_TXCMP_CODE_ERROR;
}
/* Inline or not inline - that's the Question. */
@@ -4201,7 +4206,7 @@ mlx5_tx_burst_empw_inline(struct mlx5_txq_data *restrict txq,
* No pointer and inline descriptor
* intermix for legacy MPW sessions.
*/
- if (loc->wqe_last->dseg[0].bcount)
+ if (wqem->dseg[0].bcount)
break;
}
} else {
@@ -4249,7 +4254,7 @@ mlx5_tx_burst_empw_inline(struct mlx5_txq_data *restrict txq,
*/
if (MLX5_TXOFF_CONFIG(MPW) &&
part != room &&
- loc->wqe_last->dseg[0].bcount == RTE_BE32(0))
+ wqem->dseg[0].bcount == RTE_BE32(0))
break;
/*
* Not inlinable VLAN packets are
@@ -4279,7 +4284,8 @@ mlx5_tx_burst_empw_inline(struct mlx5_txq_data *restrict txq,
* continue build descriptors.
*/
part -= room;
- mlx5_tx_idone_empw(txq, loc, part, slen, olx);
+ mlx5_tx_idone_empw(txq, loc, part,
+ slen, wqem, olx);
return MLX5_TXCMP_CODE_EXIT;
}
loc->mbuf = *pkts++;
@@ -4293,7 +4299,8 @@ mlx5_tx_burst_empw_inline(struct mlx5_txq_data *restrict txq,
*/
if (ret == MLX5_TXCMP_CODE_MULTI) {
part -= room;
- mlx5_tx_idone_empw(txq, loc, part, slen, olx);
+ mlx5_tx_idone_empw(txq, loc, part,
+ slen, wqem, olx);
if (unlikely(!loc->elts_free ||
!loc->wqe_free))
return MLX5_TXCMP_CODE_EXIT;
@@ -4302,7 +4309,8 @@ mlx5_tx_burst_empw_inline(struct mlx5_txq_data *restrict txq,
assert(NB_SEGS(loc->mbuf) == 1);
if (ret == MLX5_TXCMP_CODE_TSO) {
part -= room;
- mlx5_tx_idone_empw(txq, loc, part, slen, olx);
+ mlx5_tx_idone_empw(txq, loc, part,
+ slen, wqem, olx);
if (unlikely(!loc->elts_free ||
!loc->wqe_free))
return MLX5_TXCMP_CODE_EXIT;
@@ -4310,7 +4318,8 @@ mlx5_tx_burst_empw_inline(struct mlx5_txq_data *restrict txq,
}
if (ret == MLX5_TXCMP_CODE_SINGLE) {
part -= room;
- mlx5_tx_idone_empw(txq, loc, part, slen, olx);
+ mlx5_tx_idone_empw(txq, loc, part,
+ slen, wqem, olx);
if (unlikely(!loc->elts_free ||
!loc->wqe_free))
return MLX5_TXCMP_CODE_EXIT;
@@ -4319,7 +4328,8 @@ mlx5_tx_burst_empw_inline(struct mlx5_txq_data *restrict txq,
if (ret != MLX5_TXCMP_CODE_EMPW) {
assert(false);
part -= room;
- mlx5_tx_idone_empw(txq, loc, part, slen, olx);
+ mlx5_tx_idone_empw(txq, loc, part,
+ slen, wqem, olx);
return MLX5_TXCMP_CODE_ERROR;
}
/* Check if we have minimal room left. */
@@ -4334,7 +4344,8 @@ mlx5_tx_burst_empw_inline(struct mlx5_txq_data *restrict txq,
* - software parser settings
* - packets length (legacy MPW only)
*/
- if (!mlx5_tx_match_empw(txq, eseg, loc, dlen, olx))
+ if (!mlx5_tx_match_empw(txq, &wqem->eseg,
+ loc, dlen, olx))
break;
/* Packet attributes match, continue the same eMPW. */
if ((uintptr_t)dseg >= (uintptr_t)txq->wqes_end)
@@ -4348,7 +4359,7 @@ mlx5_tx_burst_empw_inline(struct mlx5_txq_data *restrict txq,
part -= room;
if (unlikely(!part))
return MLX5_TXCMP_CODE_EXIT;
- mlx5_tx_idone_empw(txq, loc, part, slen, olx);
+ mlx5_tx_idone_empw(txq, loc, part, slen, wqem, olx);
if (unlikely(!loc->elts_free ||
!loc->wqe_free))
return MLX5_TXCMP_CODE_EXIT;
--
2.18.1
next reply other threads:[~2021-06-16 7:06 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-16 7:06 Viacheslav Ovsiienko [this message]
2021-06-16 7:31 ` [dpdk-stable] [PATCH v2] " Viacheslav Ovsiienko
-- strict thread matches above, loose matches on Subject: below --
2020-02-27 12:28 [dpdk-stable] [PATCH 19.11] " Viacheslav Ovsiienko
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