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From: Nithin Dabilpuram <ndabilpuram@marvell.com>
To: <dev@dpdk.org>
Cc: <jerinj@marvell.com>, <skori@marvell.com>,
	<skoteshwar@marvell.com>, <pbhagavatula@marvell.com>,
	<kirankumark@marvell.com>, <psatheesh@marvell.com>,
	<asekhar@marvell.com>, <hkalra@marvell.com>, <stable@dpdk.org>
Subject: [dpdk-stable] [PATCH v4 02/62] common/cnxk: fix batch alloc completion poll logic
Date: Wed, 23 Jun 2021 10:16:02 +0530
Message-ID: <20210623044702.4240-3-ndabilpuram@marvell.com> (raw)
In-Reply-To: <20210623044702.4240-1-ndabilpuram@marvell.com>

From: Jerin Jacob <jerinj@marvell.com>

The instruction generation was not correct due to
fact that volatile suppose to use with ccode variable
as well.

Change the logic to use gcc atomic builtin to
simplify and avoid explicit volatile from the code.

Fixes: 81af26789316 ("common/cnxk: support NPA batch alloc/free")
Cc: stable@dpdk.org

Signed-off-by: Jerin Jacob <jerinj@marvell.com>
Signed-off-by: Ashwin Sekhar T K <asekhar@marvell.com>
---
 drivers/common/cnxk/roc_npa.c |  2 +-
 drivers/common/cnxk/roc_npa.h | 30 +++++++++++++++---------------
 2 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/drivers/common/cnxk/roc_npa.c b/drivers/common/cnxk/roc_npa.c
index f1e03b7..5ba6e81 100644
--- a/drivers/common/cnxk/roc_npa.c
+++ b/drivers/common/cnxk/roc_npa.c
@@ -236,7 +236,7 @@ npa_aura_pool_pair_alloc(struct npa_lf *lf, const uint32_t block_size,
 
 	/* Block size should be cache line aligned and in range of 128B-128KB */
 	if (block_size % ROC_ALIGN || block_size < 128 ||
-	    block_size > 128 * 1024)
+	    block_size > ROC_NPA_MAX_BLOCK_SZ)
 		return NPA_ERR_INVALID_BLOCK_SZ;
 
 	pos = 0;
diff --git a/drivers/common/cnxk/roc_npa.h b/drivers/common/cnxk/roc_npa.h
index 89f5c6f..59d6223 100644
--- a/drivers/common/cnxk/roc_npa.h
+++ b/drivers/common/cnxk/roc_npa.h
@@ -8,6 +8,7 @@
 #define ROC_AURA_ID_MASK       (BIT_ULL(16) - 1)
 #define ROC_AURA_OP_LIMIT_MASK (BIT_ULL(36) - 1)
 
+#define ROC_NPA_MAX_BLOCK_SZ		   (128 * 1024)
 #define ROC_CN10K_NPA_BATCH_ALLOC_MAX_PTRS 512
 #define ROC_CN10K_NPA_BATCH_FREE_MAX_PTRS  15
 
@@ -219,6 +220,17 @@ roc_npa_aura_batch_alloc_issue(uint64_t aura_handle, uint64_t *buf,
 	return 0;
 }
 
+static inline void
+roc_npa_batch_alloc_wait(uint64_t *cache_line)
+{
+	/* Batch alloc status code is updated in bits [5:6] of the first word
+	 * of the 128 byte cache line.
+	 */
+	while (((__atomic_load_n(cache_line, __ATOMIC_RELAXED) >> 5) & 0x3) ==
+	       ALLOC_CCODE_INVAL)
+		;
+}
+
 static inline unsigned int
 roc_npa_aura_batch_alloc_count(uint64_t *aligned_buf, unsigned int num)
 {
@@ -231,17 +243,10 @@ roc_npa_aura_batch_alloc_count(uint64_t *aligned_buf, unsigned int num)
 	/* Check each ROC cache line one by one */
 	for (i = 0; i < num; i += (ROC_ALIGN >> 3)) {
 		struct npa_batch_alloc_status_s *status;
-		int ccode;
 
 		status = (struct npa_batch_alloc_status_s *)&aligned_buf[i];
 
-		/* Status is updated in first 7 bits of each 128 byte cache
-		 * line. Wait until the status gets updated.
-		 */
-		do {
-			ccode = (volatile int)status->ccode;
-		} while (ccode == ALLOC_CCODE_INVAL);
-
+		roc_npa_batch_alloc_wait(&aligned_buf[i]);
 		count += status->count;
 	}
 
@@ -261,16 +266,11 @@ roc_npa_aura_batch_alloc_extract(uint64_t *buf, uint64_t *aligned_buf,
 	/* Check each ROC cache line one by one */
 	for (i = 0; i < num; i += (ROC_ALIGN >> 3)) {
 		struct npa_batch_alloc_status_s *status;
-		int line_count, ccode;
+		int line_count;
 
 		status = (struct npa_batch_alloc_status_s *)&aligned_buf[i];
 
-		/* Status is updated in first 7 bits of each 128 byte cache
-		 * line. Wait until the status gets updated.
-		 */
-		do {
-			ccode = (volatile int)status->ccode;
-		} while (ccode == ALLOC_CCODE_INVAL);
+		roc_npa_batch_alloc_wait(&aligned_buf[i]);
 
 		line_count = status->count;
 
-- 
2.8.4


           reply	other threads:[~2021-06-23  4:47 UTC|newest]

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