From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4F27CA0C41 for ; Wed, 23 Jun 2021 10:44:01 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 00EB74003E; Wed, 23 Jun 2021 10:44:01 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mails.dpdk.org (Postfix) with ESMTP id C489F4003E; Wed, 23 Jun 2021 10:43:58 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2D6D931B; Wed, 23 Jun 2021 01:43:58 -0700 (PDT) Received: from net-arm-n1sdp.shanghai.arm.com (net-arm-n1sdp.shanghai.arm.com [10.169.208.222]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 4F3CB3F719; Wed, 23 Jun 2021 01:43:55 -0700 (PDT) From: Joyce Kong To: beilei.xing@intel.com, qi.z.zhang@intel.com, ruifeng.wang@arm.com, honnappa.nagarahalli@arm.com, bruce.richardson@intel.com, helin.zhang@intel.com Cc: dev@dpdk.org, stable@dpdk.org, nd@arm.com Date: Wed, 23 Jun 2021 03:43:34 -0500 Message-Id: <20210623084334.18158-1-joyce.kong@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20210604073405.14880-1-joyce.kong@arm.com> References: <20210604073405.14880-1-joyce.kong@arm.com> Subject: [dpdk-stable] [PATCH v2] net/i40e: add logic of processing continuous DD bits for Arm X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" For Arm platforms, reading descs can get re-ordered, then the status of DD bits will be discontinuous, so add the logic to only process continuous descs by checking DD bits. Fixes: 4861cde46116 ("i40e: new poll mode driver") Cc: stable@dpdk.org Signed-off-by: Joyce Kong Reviewed-by: Ruifeng Wang --- drivers/net/i40e/i40e_rxtx.c | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/net/i40e/i40e_rxtx.c b/drivers/net/i40e/i40e_rxtx.c index 6c58decec..86e2f083e 100644 --- a/drivers/net/i40e/i40e_rxtx.c +++ b/drivers/net/i40e/i40e_rxtx.c @@ -452,7 +452,7 @@ i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq) uint16_t pkt_len; uint64_t qword1; uint32_t rx_status; - int32_t s[I40E_LOOK_AHEAD], nb_dd; + int32_t s[I40E_LOOK_AHEAD], var, nb_dd; int32_t i, j, nb_rx = 0; uint64_t pkt_flags; uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl; @@ -482,11 +482,22 @@ i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq) I40E_RXD_QW1_STATUS_SHIFT; } - rte_smp_rmb(); + /* This barrier is to order loads of different words in the descriptor */ + rte_atomic_thread_fence(__ATOMIC_ACQUIRE); /* Compute how many status bits were set */ - for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++) - nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT); + for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++) { + var = s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT); +#ifdef RTE_ARCH_ARM + /* For Arm platforms, only compute continuous status bits */ + if (var) + nb_dd += 1; + else + break; +#else + nb_dd += var; +#endif + } nb_rx += nb_dd; -- 2.17.1