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* [dpdk-stable] [PATCH v2] vhost: fix assuming packed ring size is a power of 2
@ 2021-07-07 10:30 Maxime Coquelin
  2021-07-07 11:11 ` Jiang, Cheng1
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: Maxime Coquelin @ 2021-07-07 10:30 UTC (permalink / raw)
  To: dev, cheng1.jiang, chenbo.xia; +Cc: Maxime Coquelin, stable

Unlike split ring, packed ring does not mandate the ring size
to be a power of 2. So we have to use a modulo operation when
wrapping ring index.

Fixes: 873e8dad6f49 ("vhost: support packed ring in async datapath")
Cc: stable@dpdk.org

Signed-off-by: Maxime Coquelin <maxime.coquelin@redhat.com>
---

V2: Also fix wrapping in virtio_dev_rx_async_get_info_idx which is used
in the packed ring data path.

 lib/vhost/virtio_net.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/vhost/virtio_net.c b/lib/vhost/virtio_net.c
index b93482587c..0de5231db7 100644
--- a/lib/vhost/virtio_net.c
+++ b/lib/vhost/virtio_net.c
@@ -1470,7 +1470,7 @@ virtio_dev_rx_async_get_info_idx(uint16_t pkts_idx,
 	uint16_t vq_size, uint16_t n_inflight)
 {
 	return pkts_idx > n_inflight ? (pkts_idx - n_inflight) :
-		(vq_size - n_inflight + pkts_idx) & (vq_size - 1);
+		(vq_size - n_inflight + pkts_idx) % vq_size;
 }
 
 static __rte_always_inline void
@@ -2131,7 +2131,7 @@ uint16_t rte_vhost_poll_enqueue_completed(int vid, uint16_t queue_id,
 
 	if (vq_is_packed(dev)) {
 		for (i = 0; i < n_pkts_put; i++) {
-			from = (start_idx + i) & (vq_size - 1);
+			from = (start_idx + i) % vq_size;
 			n_buffers += pkts_info[from].nr_buffers;
 			pkts[i] = pkts_info[from].mbuf;
 		}
-- 
2.31.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2021-07-20  2:51 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2021-07-07 10:30 [dpdk-stable] [PATCH v2] vhost: fix assuming packed ring size is a power of 2 Maxime Coquelin
2021-07-07 11:11 ` Jiang, Cheng1
2021-07-12  6:53   ` Jiang, Cheng1
2021-07-12  9:16     ` Maxime Coquelin
2021-07-14  5:16 ` Xia, Chenbo
2021-07-20  2:51 ` Xia, Chenbo

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