From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id BE5BEA0C49 for ; Wed, 7 Jul 2021 14:03:41 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id B3104414FE; Wed, 7 Jul 2021 14:03:41 +0200 (CEST) Received: from NAM04-BN8-obe.outbound.protection.outlook.com (mail-bn8nam08on2087.outbound.protection.outlook.com [40.107.100.87]) by mails.dpdk.org (Postfix) with ESMTP id 6BCF2414F0; Wed, 7 Jul 2021 14:03:38 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ARfTKKZrWpF/K8EqhR2U5JPrJn8jUk3hOhJv9FacKz1aMTMZtejmvhHKD4zF+9P1fjceQ3MUva+7KUVZd9HYGmKE3dig832xF5dyvauqWELcUoK4zPAw43pPdT9c1BAISuLSNayX1ViiLmz93nNG7mNUXnCUZVZKymEfQhhQIyH5bIeZmtP0yEBy36v1gwPLrIvRfmDP5Msn/4fxkebXatElQ4xwd/xYnCXhjDb5jurU0XMBIK4qOZyOZszyT22BZrZSVTqsIsbpwtguC93837nEu20vj46I6oSlfpcJL9ul1TQ4ZwVN6xUC8xMV5K8pdEF7HT1WcYVBCWGS9Ak2yA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=wLtokPooly4aiCwixB2FPl2xmdgSVmES52beIjdCbXE=; b=bdkQFkwRGGm5TxZGJea6LODqByAyyPCag/9ix/2N/BdEUcAHjHrXCJ2OwV9PokVCWjPlE3E5Q8BCrEaxIFWXII9OgDRIvJafzODibbQCWsKHjro2ZT9Rw6SQRFRTawSZIrxv8d5F0iFL9YeLtIYKdsoXZVawI6oInlAYw5QjgRf9UCiZvh6DPMRPQ1yxF6VBV7PAqI1pIxqbqbAok/iGcRNFxsuMJs/c9AYT0Jj1vZOfA1eM3uGtFgmzTYMfkBppTt/61azIkzeIFilMTdZzU+VRq+XsrHakKZf98HgPWhTjdZF7Y/+NwdhgvfKc+BBW7oSue4LPRKfQyfcO1Zd7hQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=wLtokPooly4aiCwixB2FPl2xmdgSVmES52beIjdCbXE=; b=GEzf7LxB118OZaznsKX2v0HLa4bQl4+YQRkxuoJubjmNvG3aozsL95F01SRDqYWP3joIJ4umf02dqrJcwbckuoRpi+36tFGJWJFIgs4+Z/h8kJNVv0y2yUCjvCWFuKvvVAiQEIcsuWxD3CJLmEKcyzP+38C6Yv6jdo2BQSx7+eP8RqsvojmNTSd1lGJhzTx4bA7ZGnCkzveHptb5nK2YRHaw2mdwxBObzskWBA0yMucJYqqpfg054OnWAw42KpI1vuRS38UHdAtgc8b2kt2UFaG1QbEVagXkC/qIB0x5zekBVGe3k+cVDF+gqjdAAK5v6Vqj9VRYVKuUOjuJOULzKw== Received: from BN0PR03CA0059.namprd03.prod.outlook.com (2603:10b6:408:e7::34) by BN9PR12MB5381.namprd12.prod.outlook.com (2603:10b6:408:102::24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4287.23; Wed, 7 Jul 2021 12:03:36 +0000 Received: from BN8NAM11FT015.eop-nam11.prod.protection.outlook.com (2603:10b6:408:e7:cafe::35) by BN0PR03CA0059.outlook.office365.com (2603:10b6:408:e7::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4308.20 via Frontend Transport; Wed, 7 Jul 2021 12:03:36 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.112.34) smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT015.mail.protection.outlook.com (10.13.176.90) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4308.20 via Frontend Transport; Wed, 7 Jul 2021 12:03:36 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 7 Jul 2021 12:03:34 +0000 From: Michael Baum To: CC: Matan Azrad , Raslan Darawsheh , Viacheslav Ovsiienko , Date: Wed, 7 Jul 2021 15:03:01 +0300 Message-ID: <20210707120303.2490006-2-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210707120303.2490006-1-michaelba@nvidia.com> References: <20210705052730.2283962-1-michaelba@nvidia.com> <20210707120303.2490006-1-michaelba@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 9f2feced-ad64-4271-b10c-08d9413f4052 X-MS-TrafficTypeDiagnostic: BN9PR12MB5381: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: JRZCFHXOdj1aMeSiOEjybE0qtWu/O7QzE0PhIRjPGU+Y8RUYHESltvNN72ku9tQJC1996jXTUdmJphQ7FwUOziG/NjQDjXO7JngOMu/DJEZNLTlS99f1NUD7r5fzNEhNuMsIJEtWYGXcHlxF0Vsm9tc5q9QSVxAPG9yYP7M4l8hfnZ6sRuopHvMKxSRDFndCoWxA8biPKgkXjZQXEDVyo99XH52fq33JZl2Cg+rZTIwZsW20rZWWPDsCCC+S2Gj57oegIxUPYTwpjGg8Mg0eTHSi8GoSwdRcUxzkpVVl5AGbpwfMn2Z5iyB75YBJ5lA0wRuzgRD2etbbBsZg17sPAOEoyXSV7+Sd1FkIQgALcqzmRY9wh5Xt+Gyt0hwigoXhVV+XtsQ1rlMGKtdNH6wcMefip2m8jCKj/Lj0cb4SFfBaozVKbS2HIcCeefBOcQCKTbEmHd3J/CUQTXNYKQHvnfIa0rL2D1sxRiK+MT6ppIDVAilA6pZCOHCIDW4SPfD11nZRJmH0JEJadXQMqK96Y6PYSVubiakDuGM2u+OuuN4AHOUwSI3gd8j24Vu0M6D6ANBQ0QRXxAoS5XrcxodKcdidBNzymcJ54KbIXGvTBnjH3nqahXuQxEvBVC/3joAaguEkipdmGgB1pp5yfJcGhB5zJwWTPFAbDi2ElgqpgdAyRFnCcsWHPLPhG+Lt1Jx3KWWAZVlGnTXV52OZAFXH/A== X-Forefront-Antispam-Report: CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(39860400002)(396003)(136003)(376002)(346002)(46966006)(36840700001)(7636003)(316002)(36906005)(450100002)(6666004)(5660300002)(26005)(70206006)(186003)(82740400003)(54906003)(55016002)(8936002)(6286002)(6916009)(16526019)(7696005)(8676002)(4326008)(47076005)(2906002)(1076003)(2616005)(36756003)(83380400001)(82310400003)(86362001)(426003)(36860700001)(478600001)(336012)(70586007)(356005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Jul 2021 12:03:36.5663 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9f2feced-ad64-4271-b10c-08d9413f4052 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT015.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5381 Subject: [dpdk-stable] [PATCH_v3 1/3] regex/mlx5: fix memory region unregistration X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" The issue can cause illegal physical address access while a huge-page A is released and huge-page B is allocated on the same virtual address. The old MR can be matched using the virtual address of huge-page B but the HW will access the physical address of huge-page A which is no more part of the DPDK process. Register a driver callback for memory event in order to free out all the MRs of memory that is going to be freed from the dpdk process. Fixes: cda883bbb655 ("regex/mlx5: add dynamic memory registration to datapath") Cc: stable@dpdk.org Signed-off-by: Michael Baum --- drivers/regex/mlx5/mlx5_regex.c | 55 ++++++++++++++++++++++++ drivers/regex/mlx5/mlx5_regex.h | 2 + drivers/regex/mlx5/mlx5_regex_control.c | 2 + drivers/regex/mlx5/mlx5_regex_fastpath.c | 50 +++++++++++++++------ 4 files changed, 97 insertions(+), 12 deletions(-) diff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c index dcb2ced88e..0f12d94d7e 100644 --- a/drivers/regex/mlx5/mlx5_regex.c +++ b/drivers/regex/mlx5/mlx5_regex.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include @@ -24,6 +25,10 @@ int mlx5_regex_logtype; +TAILQ_HEAD(regex_mem_event, mlx5_regex_priv) mlx5_mem_event_list = + TAILQ_HEAD_INITIALIZER(mlx5_mem_event_list); +static pthread_mutex_t mem_event_list_lock = PTHREAD_MUTEX_INITIALIZER; + const struct rte_regexdev_ops mlx5_regexdev_ops = { .dev_info_get = mlx5_regex_info_get, .dev_configure = mlx5_regex_configure, @@ -82,6 +87,40 @@ mlx5_regex_get_name(char *name, struct rte_pci_device *pci_dev __rte_unused) pci_dev->addr.devid, pci_dev->addr.function); } +/** + * Callback for memory event. + * + * @param event_type + * Memory event type. + * @param addr + * Address of memory. + * @param len + * Size of memory. + */ +static void +mlx5_regex_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr, + size_t len, void *arg __rte_unused) +{ + struct mlx5_regex_priv *priv; + + /* Must be called from the primary process. */ + MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); + switch (event_type) { + case RTE_MEM_EVENT_FREE: + pthread_mutex_lock(&mem_event_list_lock); + /* Iterate all the existing mlx5 devices. */ + TAILQ_FOREACH(priv, &mlx5_mem_event_list, mem_event_cb) + mlx5_free_mr_by_addr(&priv->mr_scache, + priv->ctx->device->name, + addr, len); + pthread_mutex_unlock(&mem_event_list_lock); + break; + case RTE_MEM_EVENT_ALLOC: + default: + break; + } +} + static int mlx5_regex_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, struct rte_pci_device *pci_dev) @@ -193,6 +232,15 @@ mlx5_regex_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, rte_errno = ENOMEM; goto error; } + /* Register callback function for global shared MR cache management. */ + if (TAILQ_EMPTY(&mlx5_mem_event_list)) + rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", + mlx5_regex_mr_mem_event_cb, + NULL); + /* Add device to memory callback list. */ + pthread_mutex_lock(&mem_event_list_lock); + TAILQ_INSERT_TAIL(&mlx5_mem_event_list, priv, mem_event_cb); + pthread_mutex_unlock(&mem_event_list_lock); DRV_LOG(INFO, "RegEx GGA is %s.", priv->has_umr ? "supported" : "unsupported"); return 0; @@ -225,6 +273,13 @@ mlx5_regex_pci_remove(struct rte_pci_device *pci_dev) return 0; priv = dev->data->dev_private; if (priv) { + /* Remove from memory callback device list. */ + pthread_mutex_lock(&mem_event_list_lock); + TAILQ_REMOVE(&mlx5_mem_event_list, priv, mem_event_cb); + pthread_mutex_unlock(&mem_event_list_lock); + if (TAILQ_EMPTY(&mlx5_mem_event_list)) + rte_mem_event_callback_unregister("MLX5_MEM_EVENT_CB", + NULL); if (priv->pd) mlx5_glue->dealloc_pd(priv->pd); if (priv->uar) diff --git a/drivers/regex/mlx5/mlx5_regex.h b/drivers/regex/mlx5/mlx5_regex.h index 51a2101e53..61f59ba873 100644 --- a/drivers/regex/mlx5/mlx5_regex.h +++ b/drivers/regex/mlx5/mlx5_regex.h @@ -70,6 +70,8 @@ struct mlx5_regex_priv { uint32_t nb_engines; /* Number of RegEx engines. */ struct mlx5dv_devx_uar *uar; /* UAR object. */ struct ibv_pd *pd; + TAILQ_ENTRY(mlx5_regex_priv) mem_event_cb; + /**< Called by memory event callback. */ struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */ uint8_t is_bf2; /* The device is BF2 device. */ uint8_t sq_ts_format; /* Whether SQ supports timestamp formats. */ diff --git a/drivers/regex/mlx5/mlx5_regex_control.c b/drivers/regex/mlx5/mlx5_regex_control.c index eef0fe579d..8ce2dabb55 100644 --- a/drivers/regex/mlx5/mlx5_regex_control.c +++ b/drivers/regex/mlx5/mlx5_regex_control.c @@ -246,6 +246,8 @@ mlx5_regex_qp_setup(struct rte_regexdev *dev, uint16_t qp_ind, nb_sq_config++; } + /* Save pointer of global generation number to check memory event. */ + qp->mr_ctrl.dev_gen_ptr = &priv->mr_scache.dev_gen; ret = mlx5_mr_btree_init(&qp->mr_ctrl.cache_bh, MLX5_MR_BTREE_CACHE_N, rte_socket_id()); if (ret) { diff --git a/drivers/regex/mlx5/mlx5_regex_fastpath.c b/drivers/regex/mlx5/mlx5_regex_fastpath.c index b57e7d7794..6d5096701f 100644 --- a/drivers/regex/mlx5/mlx5_regex_fastpath.c +++ b/drivers/regex/mlx5/mlx5_regex_fastpath.c @@ -109,6 +109,40 @@ set_wqe_ctrl_seg(struct mlx5_wqe_ctrl_seg *seg, uint16_t pi, uint8_t opcode, seg->imm = imm; } +/** + * Query LKey from a packet buffer for QP. If not found, add the mempool. + * + * @param priv + * Pointer to the priv object. + * @param mr_ctrl + * Pointer to per-queue MR control structure. + * @param mbuf + * Pointer to source mbuf, to search in. + * + * @return + * Searched LKey on success, UINT32_MAX on no match. + */ +static inline uint32_t +mlx5_regex_addr2mr(struct mlx5_regex_priv *priv, struct mlx5_mr_ctrl *mr_ctrl, + struct rte_mbuf *mbuf) +{ + uintptr_t addr = rte_pktmbuf_mtod(mbuf, uintptr_t); + uint32_t lkey; + + /* Check generation bit to see if there's any change on existing MRs. */ + if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen)) + mlx5_mr_flush_local_cache(mr_ctrl); + /* Linear search on MR cache array. */ + lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru, + MLX5_MR_CACHE_N, addr); + if (likely(lkey != UINT32_MAX)) + return lkey; + /* Take slower bottom-half on miss. */ + return mlx5_mr_addr2mr_bh(priv->pd, 0, &priv->mr_scache, mr_ctrl, addr, + !!(mbuf->ol_flags & EXT_ATTACHED_MBUF)); +} + + static inline void __prep_one(struct mlx5_regex_priv *priv, struct mlx5_regex_sq *sq, struct rte_regex_ops *op, struct mlx5_regex_job *job, @@ -160,10 +194,7 @@ prep_one(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp, struct mlx5_klm klm; klm.byte_count = rte_pktmbuf_data_len(op->mbuf); - klm.mkey = mlx5_mr_addr2mr_bh(priv->pd, 0, - &priv->mr_scache, &qp->mr_ctrl, - rte_pktmbuf_mtod(op->mbuf, uintptr_t), - !!(op->mbuf->ol_flags & EXT_ATTACHED_MBUF)); + klm.mkey = mlx5_regex_addr2mr(priv, &qp->mr_ctrl, op->mbuf); klm.address = rte_pktmbuf_mtod(op->mbuf, uintptr_t); __prep_one(priv, sq, op, job, sq->pi, &klm); sq->db_pi = sq->pi; @@ -329,10 +360,8 @@ prep_regex_umr_wqe_set(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp, (qp->jobs[mkey_job_id].imkey->id); while (mbuf) { /* Build indirect mkey seg's KLM. */ - mkey_klm->mkey = mlx5_mr_addr2mr_bh(priv->pd, - NULL, &priv->mr_scache, &qp->mr_ctrl, - rte_pktmbuf_mtod(mbuf, uintptr_t), - !!(mbuf->ol_flags & EXT_ATTACHED_MBUF)); + mkey_klm->mkey = mlx5_regex_addr2mr + (priv, &qp->mr_ctrl, mbuf); mkey_klm->address = rte_cpu_to_be_64 (rte_pktmbuf_mtod(mbuf, uintptr_t)); mkey_klm->byte_count = rte_cpu_to_be_32 @@ -350,10 +379,7 @@ prep_regex_umr_wqe_set(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp, klm.byte_count = scatter_size; } else { /* The single mubf case. Build the KLM directly. */ - klm.mkey = mlx5_mr_addr2mr_bh(priv->pd, NULL, - &priv->mr_scache, &qp->mr_ctrl, - rte_pktmbuf_mtod(mbuf, uintptr_t), - !!(mbuf->ol_flags & EXT_ATTACHED_MBUF)); + klm.mkey = mlx5_regex_addr2mr(priv, &qp->mr_ctrl, mbuf); klm.address = rte_pktmbuf_mtod(mbuf, uintptr_t); klm.byte_count = rte_pktmbuf_data_len(mbuf); } -- 2.25.1