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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by CO1NAM11FT027.mail.protection.outlook.com (10.13.174.224) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4308.20 via Frontend Transport; Mon, 12 Jul 2021 07:19:59 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 12 Jul 2021 07:19:57 +0000 From: Michael Baum To: CC: Matan Azrad , Date: Mon, 12 Jul 2021 10:19:34 +0300 Message-ID: <20210712071934.2892062-1-michaelba@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210701071807.2018505-1-michaelba@nvidia.com> References: <20210701071807.2018505-1-michaelba@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f6fd5130-a104-4d6b-21a0-08d94505755b X-MS-TrafficTypeDiagnostic: MWHPR1201MB0096: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2512; 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SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(346002)(39860400002)(136003)(376002)(396003)(36840700001)(46966006)(4326008)(1076003)(36906005)(450100002)(7696005)(8676002)(70586007)(6286002)(54906003)(186003)(70206006)(5660300002)(86362001)(316002)(82740400003)(6916009)(6666004)(478600001)(16526019)(55016002)(26005)(7636003)(8936002)(83380400001)(34020700004)(36860700001)(82310400003)(336012)(2906002)(36756003)(2616005)(47076005)(426003)(356005); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jul 2021 07:19:59.4566 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f6fd5130-a104-4d6b-21a0-08d94505755b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT027.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR1201MB0096 Subject: [dpdk-stable] [PATCH v2] compress/mlx5: fix memory region unregistration X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" The issue can cause illegal physical address access while a huge-page A is released and huge-page B is allocated on the same virtual address. The old MR can be matched using the virtual address of huge-page B but the HW will access the physical address of huge-page A which is no more part of the DPDK process. Register a driver callback for memory event in order to free out all the MRs of memory that is going to be freed from the dpdk process. Fixes: f8c97babc9f4 ("compress/mlx5: add data-path functions") Cc: stable@dpdk.org Signed-off-by: Michael Baum Acked-by: Matan Azrad --- v2: Rebase after integrating the patch on which it is based (https://patchwork.dpdk.org/project/dpdk/patch/20210628150614.1769507-1-michaelba@nvidia.com/). drivers/compress/mlx5/mlx5_compress.c | 83 ++++++++++++++++++++++++++- 1 file changed, 80 insertions(+), 3 deletions(-) diff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c index 80c564f10b..f5f51c0ebe 100644 --- a/drivers/compress/mlx5/mlx5_compress.c +++ b/drivers/compress/mlx5/mlx5_compress.c @@ -258,6 +258,8 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id, DRV_LOG(ERR, "Can't change SQ state to ready."); goto err; } + /* Save pointer of global generation number to check memory event. */ + qp->mr_ctrl.dev_gen_ptr = &priv->mr_scache.dev_gen; DRV_LOG(INFO, "QP %u: SQN=0x%X CQN=0x%X entries num = %u", (uint32_t)qp_id, qp->sq.sq->id, qp->cq.cq->id, qp->entries_n); return 0; @@ -428,6 +430,40 @@ static struct rte_compressdev_ops mlx5_compress_ops = { .stream_free = NULL, }; +/** + * Query LKey from a packet buffer for QP. If not found, add the mempool. + * + * @param priv + * Pointer to the priv object. + * @param addr + * Search key. + * @param mr_ctrl + * Pointer to per-queue MR control structure. + * @param ol_flags + * Mbuf offload features. + * + * @return + * Searched LKey on success, UINT32_MAX on no match. + */ +static __rte_always_inline uint32_t +mlx5_compress_addr2mr(struct mlx5_compress_priv *priv, uintptr_t addr, + struct mlx5_mr_ctrl *mr_ctrl, uint64_t ol_flags) +{ + uint32_t lkey; + + /* Check generation bit to see if there's any change on existing MRs. */ + if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen)) + mlx5_mr_flush_local_cache(mr_ctrl); + /* Linear search on MR cache array. */ + lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru, + MLX5_MR_CACHE_N, addr); + if (likely(lkey != UINT32_MAX)) + return lkey; + /* Take slower bottom-half on miss. */ + return mlx5_mr_addr2mr_bh(priv->pd, 0, &priv->mr_scache, mr_ctrl, addr, + !!(ol_flags & EXT_ATTACHED_MBUF)); +} + static __rte_always_inline uint32_t mlx5_compress_dseg_set(struct mlx5_compress_qp *qp, volatile struct mlx5_wqe_dseg *restrict dseg, @@ -437,9 +473,8 @@ mlx5_compress_dseg_set(struct mlx5_compress_qp *qp, uintptr_t addr = rte_pktmbuf_mtod_offset(mbuf, uintptr_t, offset); dseg->bcount = rte_cpu_to_be_32(len); - dseg->lkey = mlx5_mr_addr2mr_bh(qp->priv->pd, 0, &qp->priv->mr_scache, - &qp->mr_ctrl, addr, - !!(mbuf->ol_flags & EXT_ATTACHED_MBUF)); + dseg->lkey = mlx5_compress_addr2mr(qp->priv, addr, &qp->mr_ctrl, + mbuf->ol_flags); dseg->pbuf = rte_cpu_to_be_64(addr); return dseg->lkey; } @@ -711,6 +746,40 @@ mlx5_compress_hw_global_prepare(struct mlx5_compress_priv *priv) return 0; } +/** + * Callback for memory event. + * + * @param event_type + * Memory event type. + * @param addr + * Address of memory. + * @param len + * Size of memory. + */ +static void +mlx5_compress_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr, + size_t len, void *arg __rte_unused) +{ + struct mlx5_compress_priv *priv; + + /* Must be called from the primary process. */ + MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); + switch (event_type) { + case RTE_MEM_EVENT_FREE: + pthread_mutex_lock(&priv_list_lock); + /* Iterate all the existing mlx5 devices. */ + TAILQ_FOREACH(priv, &mlx5_compress_priv_list, next) + mlx5_free_mr_by_addr(&priv->mr_scache, + priv->ctx->device->name, + addr, len); + pthread_mutex_unlock(&priv_list_lock); + break; + case RTE_MEM_EVENT_ALLOC: + default: + break; + } +} + /** * DPDK callback to register a PCI device. * @@ -804,6 +873,11 @@ mlx5_compress_pci_probe(struct rte_pci_driver *pci_drv, } priv->mr_scache.reg_mr_cb = mlx5_common_verbs_reg_mr; priv->mr_scache.dereg_mr_cb = mlx5_common_verbs_dereg_mr; + /* Register callback function for global shared MR cache management. */ + if (TAILQ_EMPTY(&mlx5_compress_priv_list)) + rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", + mlx5_compress_mr_mem_event_cb, + NULL); pthread_mutex_lock(&priv_list_lock); TAILQ_INSERT_TAIL(&mlx5_compress_priv_list, priv, next); pthread_mutex_unlock(&priv_list_lock); @@ -834,6 +908,9 @@ mlx5_compress_pci_remove(struct rte_pci_device *pdev) TAILQ_REMOVE(&mlx5_compress_priv_list, priv, next); pthread_mutex_unlock(&priv_list_lock); if (priv) { + if (TAILQ_EMPTY(&mlx5_compress_priv_list)) + rte_mem_event_callback_unregister("MLX5_MEM_EVENT_CB", + NULL); mlx5_mr_release_cache(&priv->mr_scache); mlx5_compress_hw_global_release(priv); rte_compressdev_pmd_destroy(priv->cdev); -- 2.25.1