From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5AC6BA0C4C for ; Mon, 12 Jul 2021 15:16:06 +0200 (CEST) Received: from [217.70.189.124] (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 5281040685; Mon, 12 Jul 2021 15:16:06 +0200 (CEST) Received: from mail-wr1-f53.google.com (mail-wr1-f53.google.com [209.85.221.53]) by mails.dpdk.org (Postfix) with ESMTP id 0E41F40685 for ; Mon, 12 Jul 2021 15:16:05 +0200 (CEST) Received: by mail-wr1-f53.google.com with SMTP id d12so24941685wre.13 for ; Mon, 12 Jul 2021 06:16:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CYLSJ60Hvgozgpk/BMnTKD56jtRiHQMMrBHvIKIq2IU=; b=f+LJJLSTNb2o1ygF6H2qKE+DRHFyCXuusa7hRBMkXpySkf+xpiUbUFKN1ZE0wHxFWN VD1uBTq7v4SAnaM36IGcUhWRe9L2hyrjlxs5t9ShdbJwjP5vPCn7R4KKMvJpsTctuZsf Pkb5Yhf0HGZ5JBQyqDkBa0wMonYPfGOmHLyv8+6lEn8NVRgSu1TLXcbFMqikr8Il4ooT oajuc+sbsCiQ+mHv0LyY9ft8aHmifyO+96iYIA0xc7aBwYUKGEXQZkKlPj04SSPrTqpx pA+81cLmRXxwSdIoXcxBGhk/3VRP1XH+35YeaauoCC3i1vN0FwQJ7bwPjNQg4IcK/gTR o40g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CYLSJ60Hvgozgpk/BMnTKD56jtRiHQMMrBHvIKIq2IU=; b=B1FUB+WUGtcTmYR3b2n17A6Tg82Jd59J0yRMxLHh19pDroIhKJg//y00ij6slI8HaE AvGUWvbO6qdRJsMgU9J1UYxh0P6zEQGxf+nh0wsDNejz0y1PFZQ+Ft5lB1Esar8J6Ys7 SRbg7sMFWYU2KeZAtLeCWkD9ehxF6CzGFHNk/nB4DTXzgzDRIzXFZIggr4Hl8+wYzE7F EoXdcPkhqsQMnXmeYYP46eVHF6JjcfWTqEIEIU33mbyaYSPYp0/N6T/igYfnillj3h4A wuMr7sc9xFasM162niJqW9b/H6Po6Jqs2hBgLVmBJpDbZ2uv2x/GDvu1VUVFv9DQ2qZm PePw== X-Gm-Message-State: AOAM532bg6fFwwj5hBRXOwJIvmJzMCvsvF056nRYc4nZAwe8eUEeOoyn a9pUbxRdBoMzkaurdD0FRbc= X-Google-Smtp-Source: ABdhPJxeGikSxRyE2/GqmrX2/7VAgdAm0Fjn8J5yzjVFjzrFfRafT4Z/Qh9OQvlA9a+qkHL6+Vewcw== X-Received: by 2002:a5d:4c50:: with SMTP id n16mr59194377wrt.249.1626095764812; Mon, 12 Jul 2021 06:16:04 -0700 (PDT) Received: from localhost ([137.220.125.106]) by smtp.gmail.com with ESMTPSA id g138sm7790402wmg.32.2021.07.12.06.16.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Jul 2021 06:16:04 -0700 (PDT) From: luca.boccassi@gmail.com To: Chengwen Feng Cc: Ruifeng Wang , dpdk stable Date: Mon, 12 Jul 2021 14:05:50 +0100 Message-Id: <20210712130551.2462159-115-luca.boccassi@gmail.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210712130551.2462159-1-luca.boccassi@gmail.com> References: <20210712130551.2462159-1-luca.boccassi@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-stable] patch 'net/hns3: fix Arm SVE build with GCC 8.3' has been queued to stable release 20.11.3 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" Hi, FYI, your patch has been queued to stable release 20.11.3 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 07/14/21. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/bluca/dpdk-stable This queued commit can be viewed at: https://github.com/bluca/dpdk-stable/commit/4b81426f9edf612ee933c2d7ecb48994404d0311 Thanks. Luca Boccassi --- >From 4b81426f9edf612ee933c2d7ecb48994404d0311 Mon Sep 17 00:00:00 2001 From: Chengwen Feng Date: Mon, 28 Jun 2021 10:57:51 +0800 Subject: [PATCH] net/hns3: fix Arm SVE build with GCC 8.3 [ upstream commit 699fa1d40eeabe086d4491a0b4edd7a0a19e6aa7 ] If the target machine has SVE feature (e.g. '-march=armv8.2-a+sve'), and compiler is gcc-8.3, it will fail, the error is arm_sve.h: no such file or directory. The solution: a. If RTE_HAS_SVE_ACLE defined (it means the minimum instruction set support SVE ACLE) then compiles it. b. Else if the compiler support SVE ACLE then compiles it. c. Otherwise don't compile it. Fixes: 8c25b02b082a ("net/hns3: fix enabling SVE Rx/Tx") Fixes: 952ebacce4f2 ("net/hns3: support SVE Rx") Signed-off-by: Chengwen Feng Acked-by: Ruifeng Wang --- drivers/net/hns3/hns3_rxtx.c | 2 +- drivers/net/hns3/meson.build | 20 +++++++++++++++++++- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index c77c828011..2a92b1cf49 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -2561,7 +2561,7 @@ hns3_get_default_vec_support(void) static bool hns3_check_sve_support(void) { -#if defined(RTE_ARCH_ARM64) && defined(__ARM_FEATURE_SVE) +#if defined(RTE_HAS_SVE_ACLE) if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_SVE)) return true; #endif diff --git a/drivers/net/hns3/meson.build b/drivers/net/hns3/meson.build index 09034871e7..208527ea29 100644 --- a/drivers/net/hns3/meson.build +++ b/drivers/net/hns3/meson.build @@ -31,7 +31,25 @@ deps += ['hash'] if arch_subdir == 'arm' and dpdk_conf.get('RTE_ARCH_64') sources += files('hns3_rxtx_vec.c') - if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' + + # compile SVE when: + # a. support SVE in minimum instruction set baseline + # b. it's not minimum instruction set, but compiler support + if dpdk_conf.has('RTE_HAS_SVE_ACLE') sources += files('hns3_rxtx_vec_sve.c') + elif cc.has_argument('-march=armv8.2-a+sve') and cc.check_header('arm_sve.h') + cflags += ['-DRTE_HAS_SVE_ACLE=1'] + sve_cflags = [] + foreach flag: cflags + if not (flag.startswith('-march=') or flag.startswith('-mcpu=') or flag.startswith('-mtune=')) + sve_cflags += flag + endif + endforeach + hns3_sve_lib = static_library('hns3_sve_lib', + 'hns3_rxtx_vec_sve.c', + dependencies: [static_rte_ethdev], + include_directories: includes, + c_args: [sve_cflags, '-march=armv8.2-a+sve']) + objs += hns3_sve_lib.extract_objects('hns3_rxtx_vec_sve.c') endif endif -- 2.30.2 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2021-07-12 13:41:42.552345273 +0100 +++ 0115-net-hns3-fix-Arm-SVE-build-with-GCC-8.3.patch 2021-07-12 13:41:36.934131859 +0100 @@ -1 +1 @@ -From 699fa1d40eeabe086d4491a0b4edd7a0a19e6aa7 Mon Sep 17 00:00:00 2001 +From 4b81426f9edf612ee933c2d7ecb48994404d0311 Mon Sep 17 00:00:00 2001 @@ -5,0 +6,2 @@ +[ upstream commit 699fa1d40eeabe086d4491a0b4edd7a0a19e6aa7 ] + @@ -18 +19,0 @@ -Cc: stable@dpdk.org @@ -28 +29 @@ -index cb9eccf9fa..a86e105fbc 100644 +index c77c828011..2a92b1cf49 100644 @@ -31 +32 @@ -@@ -2811,7 +2811,7 @@ hns3_get_default_vec_support(void) +@@ -2561,7 +2561,7 @@ hns3_get_default_vec_support(void) @@ -33 +34 @@ - hns3_get_sve_support(void) + hns3_check_sve_support(void) @@ -37,2 +37,0 @@ - if (rte_vect_get_max_simd_bitwidth() < RTE_VECT_SIMD_256) - return false; @@ -39,0 +39,2 @@ + return true; + #endif @@ -41 +42 @@ -index 53c7df7daf..a99e0dbb74 100644 +index 09034871e7..208527ea29 100644 @@ -44 +45 @@ -@@ -35,7 +35,25 @@ deps += ['hash'] +@@ -31,7 +31,25 @@ deps += ['hash'] @@ -47,2 +48,2 @@ - sources += files('hns3_rxtx_vec.c') -- if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' + sources += files('hns3_rxtx_vec.c') +- if cc.get_define('__ARM_FEATURE_SVE', args: machine_args) != '' @@ -50,20 +51,20 @@ -+ # compile SVE when: -+ # a. support SVE in minimum instruction set baseline -+ # b. it's not minimum instruction set, but compiler support -+ if dpdk_conf.has('RTE_HAS_SVE_ACLE') - sources += files('hns3_rxtx_vec_sve.c') -+ elif cc.has_argument('-march=armv8.2-a+sve') and cc.check_header('arm_sve.h') -+ cflags += ['-DRTE_HAS_SVE_ACLE=1'] -+ sve_cflags = [] -+ foreach flag: cflags -+ if not (flag.startswith('-march=') or flag.startswith('-mcpu=') or flag.startswith('-mtune=')) -+ sve_cflags += flag -+ endif -+ endforeach -+ hns3_sve_lib = static_library('hns3_sve_lib', -+ 'hns3_rxtx_vec_sve.c', -+ dependencies: [static_rte_ethdev], -+ include_directories: includes, -+ c_args: [sve_cflags, '-march=armv8.2-a+sve']) -+ objs += hns3_sve_lib.extract_objects('hns3_rxtx_vec_sve.c') - endif ++ # compile SVE when: ++ # a. support SVE in minimum instruction set baseline ++ # b. it's not minimum instruction set, but compiler support ++ if dpdk_conf.has('RTE_HAS_SVE_ACLE') + sources += files('hns3_rxtx_vec_sve.c') ++ elif cc.has_argument('-march=armv8.2-a+sve') and cc.check_header('arm_sve.h') ++ cflags += ['-DRTE_HAS_SVE_ACLE=1'] ++ sve_cflags = [] ++ foreach flag: cflags ++ if not (flag.startswith('-march=') or flag.startswith('-mcpu=') or flag.startswith('-mtune=')) ++ sve_cflags += flag ++ endif ++ endforeach ++ hns3_sve_lib = static_library('hns3_sve_lib', ++ 'hns3_rxtx_vec_sve.c', ++ dependencies: [static_rte_ethdev], ++ include_directories: includes, ++ c_args: [sve_cflags, '-march=armv8.2-a+sve']) ++ objs += hns3_sve_lib.extract_objects('hns3_rxtx_vec_sve.c') + endif