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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT050.mail.protection.outlook.com (10.13.177.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4308.20 via Frontend Transport; Tue, 13 Jul 2021 15:21:37 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 13 Jul 2021 15:21:35 +0000 From: Alexander Kozyrev To: CC: , , , Date: Tue, 13 Jul 2021 18:21:12 +0300 Message-ID: <20210713152112.393741-1-akozyrev@nvidia.com> X-Mailer: git-send-email 2.18.2 In-Reply-To: <20210712142910.314572-1-akozyrev@nvidia.com> References: <20210712142910.314572-1-akozyrev@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL107.nvidia.com (172.20.187.13) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a785fd43-ed7a-4aa2-c26b-08d94611e8aa X-MS-TrafficTypeDiagnostic: CY4PR1201MB0024: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; 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SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(376002)(39860400002)(396003)(136003)(346002)(36840700001)(46966006)(7696005)(47076005)(7636003)(8676002)(82740400003)(966005)(16526019)(336012)(356005)(6916009)(54906003)(83380400001)(26005)(70586007)(36860700001)(55016002)(70206006)(186003)(36756003)(478600001)(6286002)(1076003)(426003)(8936002)(4326008)(86362001)(450100002)(82310400003)(2616005)(34020700004)(6666004)(36906005)(5660300002)(316002)(2906002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jul 2021 15:21:37.9740 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a785fd43-ed7a-4aa2-c26b-08d94611e8aa X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT050.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR1201MB0024 Subject: [dpdk-stable] [PATCH v2] net/mlx5: fix threshold for mbuf replenishment in MPRQ X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" The replenishment scheme for the vectorized MPRQ Rx burst aims to improve the cache locality by allocating new mbufs only when there are almost no mbufs left: one burst gap between allocated and consumed indexes. This gap is not big enough to accommodate a corner case when we have a very aggressive CQE compression with multiple regular CQEs at the beginning and 64 zipped CQEs at the end. Need to keep in mind this case and extend the replenishment threshold by MLX5_VPMD_RX_MAX_BURST (64) to avoid mbuf overflow. Fixes: 5fc2e5c27d6 ("net/mlx5: fix mbuf overflow in vectorized MPRQ") Cc: stable@dpdk.org Signed-off-by: Alexander Kozyrev Acked-by: Viacheslav Ovsiienko --- v2: increased the replenishment gap to MLX5_VPMD_RX_MAX_BURST v1: https://patchwork.dpdk.org/project/dpdk/patch/20210712142910.314572-1-akozyrev@nvidia.com/ drivers/net/mlx5/mlx5_rxtx_vec.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5_rxtx_vec.c b/drivers/net/mlx5/mlx5_rxtx_vec.c index e64ef70181..e1b6d5422a 100644 --- a/drivers/net/mlx5/mlx5_rxtx_vec.c +++ b/drivers/net/mlx5/mlx5_rxtx_vec.c @@ -157,7 +157,8 @@ mlx5_rx_mprq_replenish_bulk_mbuf(struct mlx5_rxq_data *rxq) unsigned int i; if (n >= rxq->rq_repl_thresh && - rxq->elts_ci - rxq->rq_pi <= rxq->rq_repl_thresh) { + rxq->elts_ci - rxq->rq_pi <= + rxq->rq_repl_thresh + MLX5_VPMD_RX_MAX_BURST) { MLX5_ASSERT(n >= MLX5_VPMD_RXQ_RPLNSH_THRESH(elts_n)); MLX5_ASSERT(MLX5_VPMD_RXQ_RPLNSH_THRESH(elts_n) > MLX5_VPMD_DESCS_PER_LOOP); -- 2.18.2