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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT019.mail.protection.outlook.com (10.13.172.172) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4415.14 via Frontend Transport; Thu, 12 Aug 2021 11:12:39 +0000 Received: from nvidia.com (172.20.187.5) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 12 Aug 2021 11:12:37 +0000 From: Gregory Etelson To: CC: , , Date: Thu, 12 Aug 2021 14:12:23 +0300 Message-ID: <20210812111223.16226-1-getelson@nvidia.com> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 32076c5b-df0e-43ad-be94-08d95d8218ce X-MS-TrafficTypeDiagnostic: DM5PR1201MB0059: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:191; 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CAT:NONE; SFS:(4636009)(396003)(39860400002)(376002)(346002)(136003)(36840700001)(46966006)(316002)(54906003)(36906005)(6916009)(86362001)(83380400001)(1076003)(478600001)(82310400003)(82740400003)(2616005)(5660300002)(4326008)(47076005)(107886003)(7696005)(7636003)(8936002)(36860700001)(70586007)(356005)(70206006)(55016002)(26005)(426003)(8676002)(6286002)(2906002)(6666004)(16526019)(186003)(36756003)(336012)(21314003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Aug 2021 11:12:39.1040 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 32076c5b-df0e-43ad-be94-08d95d8218ce X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT019.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1201MB0059 Subject: [dpdk-stable] [PATCH 19.11] net/mlx5: fix representor interrupt handler X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" [ upstream commit 494d6863c2464838e8ee65b9a7d3d108145ae08d ] In mlx5 PMD the PCI device interrupt vector was used by Uplink representor exclusively and other VF representors did not support interrupt mode. All the VFs and Uplink representors are separate ethernet devices and must have dedicated interrupt vectors. The fix provides each representor with a dedicated interrupt vector. Fixes: 5882bde88da2 ("net/mlx5: fix representor interrupts handler") Signed-off-by: Gregory Etelson Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5.c | 30 ++++++++++++++++++++++++++++++ drivers/net/mlx5/mlx5_rxq.c | 6 ------ 2 files changed, 30 insertions(+), 6 deletions(-) diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c index 3208b2eda7..b070d9ba89 100644 --- a/drivers/net/mlx5/mlx5.c +++ b/drivers/net/mlx5/mlx5.c @@ -1334,6 +1334,11 @@ mlx5_dev_close(struct rte_eth_dev *dev) priv->rxqs_n = 0; priv->rxqs = NULL; } + if (priv->representor) { + /* Each representor has a dedicated interrupts handler */ + rte_free(dev->intr_handle); + dev->intr_handle = NULL; + } if (priv->txqs != NULL) { /* XXX race condition if mlx5_tx_burst() is still running. */ usleep(1000); @@ -3421,6 +3426,31 @@ mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, } restore = list[i].eth_dev->data->dev_flags; rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); + /** + * Each representor has a dedicated interrupts vector. + * rte_eth_copy_pci_info() assigns PF interrupts handle to + * representor eth_dev object because representor and PF + * share the same PCI address. + * Override representor device with a dedicated + * interrupts handle here. + * Representor interrupts handle is released in + * mlx5_dev_stop(). + */ + if (list[i].info.representor) { + struct rte_intr_handle *intr_handle; + intr_handle = rte_zmalloc("representor interrupts", + sizeof(*intr_handle), 0); + if (!intr_handle) { + DRV_LOG(ERR, + "port %u failed to allocate memory for interrupt handler " + "Rx interrupts will not be supported", + i); + rte_errno = ENOMEM; + ret = -rte_errno; + goto exit; + } + list[i].eth_dev->intr_handle = intr_handle; + } /* Restore non-PCI flags cleared by the above call. */ list[i].eth_dev->data->dev_flags |= restore; rte_eth_dev_probing_finish(list[i].eth_dev); diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index e3f41d121d..16466a4ef9 100644 --- a/drivers/net/mlx5/mlx5_rxq.c +++ b/drivers/net/mlx5/mlx5_rxq.c @@ -723,9 +723,6 @@ mlx5_rx_intr_vec_enable(struct rte_eth_dev *dev) unsigned int count = 0; struct rte_intr_handle *intr_handle = dev->intr_handle; - /* Representor shares dev->intr_handle with PF. */ - if (priv->representor) - return 0; if (!dev->data->dev_conf.intr_conf.rxq) return 0; mlx5_rx_intr_vec_disable(dev); @@ -803,9 +800,6 @@ mlx5_rx_intr_vec_disable(struct rte_eth_dev *dev) unsigned int rxqs_n = priv->rxqs_n; unsigned int n = RTE_MIN(rxqs_n, (uint32_t)RTE_MAX_RXTX_INTR_VEC_ID); - /* Representor shares dev->intr_handle with PF. */ - if (priv->representor) - return; if (!dev->data->dev_conf.intr_conf.rxq) return; if (!intr_handle->intr_vec) -- 2.32.0