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dpdk.org; dkim=none (message not signed) header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by DM6NAM11FT035.mail.protection.outlook.com (10.13.172.100) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4608.15 via Frontend Transport; Wed, 13 Oct 2021 17:27:03 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Wed, 13 Oct 2021 17:27:01 +0000 From: Gregory Etelson To: , CC: , , Shahaf Shuler , Viacheslav Ovsiienko , "Dekel Peled" Date: Wed, 13 Oct 2021 20:26:46 +0300 Message-ID: <20211013172646.28303-1-getelson@nvidia.com> X-Mailer: git-send-email 2.33.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL105.nvidia.com (172.20.187.12) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: ffee702a-51b6-4ece-943d-08d98e6eac70 X-MS-TrafficTypeDiagnostic: BL1PR12MB5206: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; 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CAT:NONE; SFS:(4636009)(36840700001)(46966006)(5660300002)(70586007)(70206006)(8936002)(6286002)(7049001)(8676002)(6666004)(16526019)(55016002)(316002)(508600001)(36860700001)(7696005)(36756003)(2906002)(82310400003)(83380400001)(47076005)(26005)(186003)(7636003)(54906003)(1076003)(426003)(86362001)(336012)(2616005)(356005)(4326008)(110136005)(107886003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2021 17:27:03.9112 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ffee702a-51b6-4ece-943d-08d98e6eac70 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT035.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5206 Subject: [dpdk-stable] [PATCH] [19.11] net/mlx5: fix implicit VLAN match in RSS expansions X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Sender: "stable" RSS flow rules with patterns expanded from ETH item only, do not reference VLAN header after ETH. In the expanded patterns, ETH header is followed by L3. As the result, packets with VLAN header did not match. The patch allows VLAN header after ETH in RSS expanded rules. Cc: stable@dpdk.org Fixes: 2d85e1f ("net/mlx5: fix VLAN match for DV mode") Signed-off-by: Gregory Etelson --- drivers/net/mlx5/mlx5_flow.c | 28 ++++++++++++++++++++++++++++ drivers/net/mlx5/mlx5_flow.h | 3 +++ drivers/net/mlx5/mlx5_flow_dv.c | 30 ++++++++++++++++++++++++++++++ 3 files changed, 61 insertions(+) diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index 0805bdb8c9..afcf8a1b72 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -34,6 +34,9 @@ #include "mlx5_prm.h" #include "mlx5_rxtx.h" +static void +mlx5_dbg__print_pattern(const struct rte_flow_item *item); + /* Dev ops structure defined in mlx5.c */ extern const struct eth_dev_ops mlx5_dev_ops; extern const struct eth_dev_ops mlx5_dev_ops_isolate; @@ -4317,6 +4320,11 @@ flow_list_create(struct rte_eth_dev *dev, struct mlx5_flows *list, graph_root); assert(ret > 0 && (unsigned int)ret < sizeof(expand_buffer.buffer)); + if (rte_log_get_level(mlx5_logtype) >= (int)RTE_LOG_DEBUG) { + for (i = 0; i < buf->entries; ++i) + mlx5_dbg__print_pattern(buf->entry[i].pattern); + } + } else { buf->entries = 1; buf->entry[0].pattern = (void *)(uintptr_t)items; @@ -4327,6 +4335,7 @@ flow_list_create(struct rte_eth_dev *dev, struct mlx5_flows *list, * depending on configuration. In the simplest * case it just creates unmodified original flow. */ + flow->rss_first_exp = !!(buf->entries > 1 && (i == 0)); ret = flow_create_split_outer(dev, flow, attr, buf->entry[i].pattern, p_actions_rx, external, @@ -5810,3 +5819,22 @@ mlx5_flow_discover_mreg_c(struct rte_eth_dev *dev) config->flow_mreg_c[n] = REG_NONE; return 0; } + +static void +mlx5_dbg__print_pattern(const struct rte_flow_item *item) +{ + int ret; + struct rte_flow_error error; + + for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { + char *item_name; + ret = rte_flow_conv(RTE_FLOW_CONV_OP_ITEM_NAME_PTR, &item_name, + sizeof(item_name), + (void *)(uintptr_t)item->type, &error); + if (ret > 0) + printf("%s ", item_name); + else + printf("%d\n", (int)item->type); + } + printf("END\n"); +} diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h index caf6afd4d8..83e1bbfbbd 100644 --- a/drivers/net/mlx5/mlx5_flow.h +++ b/drivers/net/mlx5/mlx5_flow.h @@ -689,6 +689,9 @@ struct rte_flow { struct mlx5_fdir *fdir; /**< Pointer to associated FDIR if any. */ uint32_t hairpin_flow_id; /**< The flow id used for hairpin. */ uint32_t copy_applied:1; /**< The MARK copy Flow os applied. */ + uint32_t rss_first_exp:1; /**< First flow in RSS expansion */ + uint32_t vlan_m:1; /**< VLAN matcher mask */ + uint32_t vlan_v:1; /**< VLAN matcher value */ }; typedef int (*mlx5_flow_validate_t)(struct rte_eth_dev *dev, diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c index f8ca36b1c6..3323c5f8df 100644 --- a/drivers/net/mlx5/mlx5_flow_dv.c +++ b/drivers/net/mlx5/mlx5_flow_dv.c @@ -7870,6 +7870,36 @@ __flow_dv_translate(struct rte_eth_dev *dev, } assert(!flow_dv_check_valid_spec(matcher.mask.buf, dev_flow->dv.value.buf)); + if (dev_flow->actions & MLX5_FLOW_ACTION_RSS) { + void *headers_m, *headers_v; + + if (flow->rss.level > 1) { + headers_m = MLX5_ADDR_OF(fte_match_param, match_mask, + inner_headers); + headers_v = MLX5_ADDR_OF(fte_match_param, match_value, + inner_headers); + } else { + headers_m = MLX5_ADDR_OF(fte_match_param, match_mask, + outer_headers); + headers_v = MLX5_ADDR_OF(fte_match_param, match_value, + outer_headers); + } + /* The first flow in RSS expansion series has the original + * pattern. + * RSS expansion matchers will use these values. + */ + if (flow->rss_first_exp) { + flow->vlan_m = MLX5_GET(fte_match_set_lyr_2_4, + headers_m, cvlan_tag); + flow->vlan_v = MLX5_GET(fte_match_set_lyr_2_4, + headers_v, cvlan_tag); + } else { + MLX5_SET(fte_match_set_lyr_2_4, headers_m, + cvlan_tag, flow->vlan_m); + MLX5_SET(fte_match_set_lyr_2_4, headers_v, + cvlan_tag, flow->vlan_v); + } + } /* * Layers may be already initialized from prefix flow if this dev_flow * is the suffix flow. -- 2.33.0