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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.112.34 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.112.34; helo=mail.nvidia.com; Received: from mail.nvidia.com (216.228.112.34) by BN8NAM11FT012.mail.protection.outlook.com (10.13.177.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.4734.22 via Frontend Transport; Sun, 28 Nov 2021 15:01:19 +0000 Received: from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.18; Sun, 28 Nov 2021 15:01:03 +0000 From: Xueming Li To: Michael Baum CC: Luca Boccassi , Viacheslav Ovsiienko , dpdk stable Subject: patch 'common/mlx5: fix user mode register access attribute' has been queued to stable release 20.11.4 Date: Sun, 28 Nov 2021 22:54:00 +0800 Message-ID: <20211128145423.3974892-57-xuemingl@nvidia.com> X-Mailer: git-send-email 2.34.0 In-Reply-To: <20211128145423.3974892-1-xuemingl@nvidia.com> References: <20211110063216.2744012-1-xuemingl@nvidia.com> <20211128145423.3974892-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [172.20.187.6] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL107.nvidia.com (172.20.187.13) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 896ea99c-bfff-45a8-15e0-08d9b27fef22 X-MS-TrafficTypeDiagnostic: DM5PR1201MB0202: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE; SFS:(4636009)(36840700001)(46966006)(2616005)(4326008)(966005)(6862004)(508600001)(36756003)(70206006)(70586007)(26005)(7636003)(55016003)(82310400004)(36860700001)(356005)(426003)(6636002)(54906003)(316002)(37006003)(8936002)(8676002)(47076005)(4001150100001)(2906002)(86362001)(6286002)(53546011)(83380400001)(1076003)(186003)(16526019)(336012)(7696005)(5660300002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Nov 2021 15:01:19.0535 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 896ea99c-bfff-45a8-15e0-08d9b27fef22 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT012.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1201MB0202 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 20.11.4 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 11/30/21. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/steevenlee/dpdk This queued commit can be viewed at: https://github.com/steevenlee/dpdk/commit/91ab2a7d0a4e14f90765380dcc37aa785392e92c Thanks. Xueming Li --- >From 91ab2a7d0a4e14f90765380dcc37aa785392e92c Mon Sep 17 00:00:00 2001 From: Michael Baum Date: Wed, 17 Nov 2021 12:57:09 +0200 Subject: [PATCH] common/mlx5: fix user mode register access attribute Cc: Xueming Li [ upstream commit e6a6829f9996b1cf066669ad1721b3d04552c048 ] To detect the timestamp mode configured on the NIC the mlx5 PMD uses the firmware command ACCESS_REGISTER_USER. The HCA capability command has an attribute flag checking whether firmware supports the command. However, the HCA capability query command read the flag from wrong place in PRM structure. This patch move the flag to correct place. Fixes: 972a1bf8120d ("common/mlx5: fix user mode register access command") Signed-off-by: Michael Baum Acked-by: Viacheslav Ovsiienko --- drivers/common/mlx5/mlx5_prm.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h index 4792835200..201224cf24 100644 --- a/drivers/common/mlx5/mlx5_prm.h +++ b/drivers/common/mlx5/mlx5_prm.h @@ -1140,13 +1140,14 @@ struct mlx5_ifc_cmd_hca_cap_bits { u8 reserved_at_bc[0x4]; u8 reserved_at_c0[0x8]; u8 log_max_cq_sz[0x8]; - u8 reserved_at_d0[0xb]; + u8 reserved_at_d0[0x2]; + u8 access_register_user[0x1]; + u8 reserved_at_d3[0x8]; u8 log_max_cq[0x5]; u8 log_max_eq_sz[0x8]; u8 relaxed_ordering_write[0x1]; u8 relaxed_ordering_read[0x1]; - u8 access_register_user[0x1]; - u8 log_max_mkey[0x5]; + u8 log_max_mkey[0x6]; u8 reserved_at_f0[0x8]; u8 dump_fill_mkey[0x1]; u8 reserved_at_f9[0x3]; -- 2.34.0 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2021-11-28 22:41:06.177175093 +0800 +++ 0056-common-mlx5-fix-user-mode-register-access-attribute.patch 2021-11-28 22:41:03.390206379 +0800 @@ -1 +1 @@ -From e6a6829f9996b1cf066669ad1721b3d04552c048 Mon Sep 17 00:00:00 2001 +From 91ab2a7d0a4e14f90765380dcc37aa785392e92c Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Xueming Li + +[ upstream commit e6a6829f9996b1cf066669ad1721b3d04552c048 ] @@ -17 +19,0 @@ -Cc: stable@dpdk.org @@ -26 +28 @@ -index 13959575e3..2ded67e85e 100644 +index 4792835200..201224cf24 100644 @@ -29 +31 @@ -@@ -1370,13 +1370,14 @@ struct mlx5_ifc_cmd_hca_cap_bits { +@@ -1140,13 +1140,14 @@ struct mlx5_ifc_cmd_hca_cap_bits {