[PATCH 1/5] doc: remove obsolete explanations from mlx5 guide

[PATCH 1/5] doc: remove obsolete explanations from mlx5 guide

[Michael Baum]

Vectorized routines were removed in result of Tx datapath refactoring,
and devarg keys documentation was updated.

However, more updating should have been done. In environment variables
doc, there was explanation according to vectorized Tx which isn't
relevant anymore.

This patch removes this irrelevant explanation.

Fixes: a6bd4911ad93 ("net/mlx5: remove Tx implementation")
Cc: stable@dpdk.org

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
 doc/guides/nics/mlx5.rst | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index c3cc0c0f41..3f5c8bb303 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -557,15 +557,6 @@ Environment variables
   The register would be flushed to HW usually when the write-combining buffer
   becomes full, but it depends on CPU design.
 
-  Except for vectorized Tx burst routines, a write memory barrier is enforced
-  after updating the register so that the update can be immediately visible to
-  HW.
-
-  When vectorized Tx burst is called, the barrier is set only if the burst size
-  is not aligned to MLX5_VPMD_TX_MAX_BURST. However, setting this environmental
-  variable will bring better latency even though the maximum throughput can
-  slightly decline.
-
 Run-time configuration
 ~~~~~~~~~~~~~~~~~~~~~~
 
-- 
2.25.1

[PATCH v2 1/5] doc: remove obsolete explanations from mlx5 guide

[Michael Baum]

Vectorized routines were removed in result of Tx datapath refactoring,
and devarg keys documentation was updated.

However, more updating should have been done. In environment variables
doc, there was explanation according to vectorized Tx which isn't
relevant anymore.

This patch removes this irrelevant explanation.

Fixes: a6bd4911ad93 ("net/mlx5: remove Tx implementation")
Cc: stable@dpdk.org

Signed-off-by: Michael Baum <michaelba@nvidia.com>
Reviewed-by: Raslan Darawsheh <rasland@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
 doc/guides/nics/mlx5.rst | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 6494f4ae39..c21df81717 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -557,15 +557,6 @@ Environment variables
   The register would be flushed to HW usually when the write-combining buffer
   becomes full, but it depends on CPU design.
 
-  Except for vectorized Tx burst routines, a write memory barrier is enforced
-  after updating the register so that the update can be immediately visible to
-  HW.
-
-  When vectorized Tx burst is called, the barrier is set only if the burst size
-  is not aligned to MLX5_VPMD_TX_MAX_BURST. However, setting this environmental
-  variable will bring better latency even though the maximum throughput can
-  slightly decline.
-
 Run-time configuration
 ~~~~~~~~~~~~~~~~~~~~~~
 
-- 
2.25.1