[PATCH 1/9] net/ngbe: fix to set force speed

[PATCH 1/9] net/ngbe: fix to set force speed

[Jiawen Wu]

Since the bit of ETH_LINK_SPEED_FIXED was set for the force link
speed, it conflicts with '~allowed_speeds'.

Fixes: 3518df5774c7 ("net/ngbe: support device start/stop")
Cc: stable@dpdk.org

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
---
 drivers/net/ngbe/ngbe_ethdev.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ngbe/ngbe_ethdev.c b/drivers/net/ngbe/ngbe_ethdev.c
index 4a2a9dde10..c7301a9616 100644
--- a/drivers/net/ngbe/ngbe_ethdev.c
+++ b/drivers/net/ngbe/ngbe_ethdev.c
@@ -1048,7 +1048,7 @@ ngbe_dev_start(struct rte_eth_dev *dev)
 	if (hw->mac.default_speeds & NGBE_LINK_SPEED_10M_FULL)
 		allowed_speeds |= RTE_ETH_LINK_SPEED_10M;
 
-	if (*link_speeds & ~allowed_speeds) {
+	if (((*link_speeds) >> 1) & ~(allowed_speeds >> 1)) {
 		PMD_INIT_LOG(ERR, "Invalid link setting");
 		goto error;
 	}
-- 
2.27.0

[PATCH 3/9] net/ngbe: fix occasional failure of reading PHY ID

[Jiawen Wu]

Change to check low ID register to determine the valid PHY address,
for yt8521s PHY with high ID register value 0. And fix polling
register when expect value is 0, to complete MDIO read.

Fixes: 44e97550ca68 ("net/ngbe: identify and reset PHY")
Cc: stable@dpdk.org

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
---
 drivers/net/ngbe/base/ngbe_phy.c  | 7 ++-----
 drivers/net/ngbe/base/ngbe_regs.h | 9 +++++++--
 2 files changed, 9 insertions(+), 7 deletions(-)

diff --git a/drivers/net/ngbe/base/ngbe_phy.c b/drivers/net/ngbe/base/ngbe_phy.c
index 8199696428..1025d7d3a1 100644
--- a/drivers/net/ngbe/base/ngbe_phy.c
+++ b/drivers/net/ngbe/base/ngbe_phy.c
@@ -120,17 +120,14 @@ bool ngbe_validate_phy_addr(struct ngbe_hw *hw, u32 phy_addr)
 	u16 phy_id = 0;
 	bool valid = false;
 
-	if (hw->sub_device_id == NGBE_SUB_DEV_ID_EM_YT8521S_SFP)
-		return true;
-
 	hw->phy.addr = phy_addr;
-	hw->phy.read_reg(hw, NGBE_MD_PHY_ID_HIGH,
+	hw->phy.read_reg(hw, NGBE_MD_PHY_ID_LOW,
 			     NGBE_MD_DEV_PMA_PMD, &phy_id);
 
 	if (phy_id != 0xFFFF && phy_id != 0x0)
 		valid = true;
 
-	DEBUGOUT("PHY ID HIGH is 0x%04X", phy_id);
+	DEBUGOUT("PHY ID LOW is 0x%04X", phy_id);
 
 	return valid;
 }
diff --git a/drivers/net/ngbe/base/ngbe_regs.h b/drivers/net/ngbe/base/ngbe_regs.h
index 6432ad8736..640e385990 100644
--- a/drivers/net/ngbe/base/ngbe_regs.h
+++ b/drivers/net/ngbe/base/ngbe_regs.h
@@ -1422,8 +1422,13 @@ po32m(struct ngbe_hw *hw, u32 reg, u32 mask, u32 expect, u32 *actual,
 	}
 
 	do {
-		all |= rd32(hw, reg);
-		value |= mask & all;
+		if (expect != 0) {
+			all |= rd32(hw, reg);
+			value |= mask & all;
+		} else {
+			all = rd32(hw, reg);
+			value = mask & all;
+		}
 		if (value == expect)
 			break;
 
-- 
2.27.0

[PATCH 4/9] net/ngbe: fix external PHY to power down

[Jiawen Wu]

External PHY cannot power down after LAN reset, so need to manually
power down when device stopped.

Fixes: 3d0af7066759 ("net/ngbe: setup PHY link")
Fixes: 1c44384fce76 ("net/ngbe: support custom PHY interfaces")
Cc: stable@dpdk.org

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
---
 drivers/net/ngbe/base/ngbe_dummy.h   |  5 +++
 drivers/net/ngbe/base/ngbe_phy.c     |  2 +
 drivers/net/ngbe/base/ngbe_phy_mvl.c | 23 +++++++----
 drivers/net/ngbe/base/ngbe_phy_mvl.h |  1 +
 drivers/net/ngbe/base/ngbe_phy_yt.c  | 59 +++++++++++++---------------
 drivers/net/ngbe/base/ngbe_phy_yt.h  |  2 +
 drivers/net/ngbe/ngbe_ethdev.c       | 12 ++----
 7 files changed, 57 insertions(+), 47 deletions(-)

diff --git a/drivers/net/ngbe/base/ngbe_dummy.h b/drivers/net/ngbe/base/ngbe_dummy.h
index 836206e325..dd6c2fab96 100644
--- a/drivers/net/ngbe/base/ngbe_dummy.h
+++ b/drivers/net/ngbe/base/ngbe_dummy.h
@@ -237,6 +237,10 @@ static inline s32 ngbe_phy_check_link_dummy(struct ngbe_hw *TUP0, u32 *TUP1,
 {
 	return NGBE_ERR_OPS_DUMMY;
 }
+static inline s32 ngbe_phy_set_phy_power_dummy(struct ngbe_hw *TUP0, bool TUP1)
+{
+	return NGBE_ERR_OPS_DUMMY;
+}
 static inline s32 ngbe_get_phy_advertised_pause_dummy(struct ngbe_hw *TUP0,
 					u8 *TUP1)
 {
@@ -337,6 +341,7 @@ static inline void ngbe_init_ops_dummy(struct ngbe_hw *hw)
 	hw->phy.get_lp_adv_pause = ngbe_get_phy_lp_advertised_pause_dummy;
 	hw->phy.set_pause_adv = ngbe_set_phy_pause_adv_dummy;
 	hw->phy.led_oem_chk = ngbe_phy_led_oem_chk_dummy;
+	hw->phy.set_phy_power = ngbe_phy_set_phy_power_dummy;
 	hw->mbx.init_params = ngbe_mbx_init_params_dummy;
 	hw->mbx.read = ngbe_mbx_read_dummy;
 	hw->mbx.write = ngbe_mbx_write_dummy;
diff --git a/drivers/net/ngbe/base/ngbe_phy.c b/drivers/net/ngbe/base/ngbe_phy.c
index 1025d7d3a1..84f2925e7e 100644
--- a/drivers/net/ngbe/base/ngbe_phy.c
+++ b/drivers/net/ngbe/base/ngbe_phy.c
@@ -421,6 +421,7 @@ s32 ngbe_init_phy(struct ngbe_hw *hw)
 		hw->phy.init_hw = ngbe_init_phy_mvl;
 		hw->phy.check_link = ngbe_check_phy_link_mvl;
 		hw->phy.setup_link = ngbe_setup_phy_link_mvl;
+		hw->phy.set_phy_power = ngbe_set_phy_power_mvl;
 		hw->phy.get_adv_pause = ngbe_get_phy_advertised_pause_mvl;
 		hw->phy.get_lp_adv_pause = ngbe_get_phy_lp_advertised_pause_mvl;
 		hw->phy.set_pause_adv = ngbe_set_phy_pause_adv_mvl;
@@ -430,6 +431,7 @@ s32 ngbe_init_phy(struct ngbe_hw *hw)
 		hw->phy.init_hw = ngbe_init_phy_yt;
 		hw->phy.check_link = ngbe_check_phy_link_yt;
 		hw->phy.setup_link = ngbe_setup_phy_link_yt;
+		hw->phy.set_phy_power = ngbe_set_phy_power_yt;
 		hw->phy.get_adv_pause = ngbe_get_phy_advertised_pause_yt;
 		hw->phy.get_lp_adv_pause = ngbe_get_phy_lp_advertised_pause_yt;
 		hw->phy.set_pause_adv = ngbe_set_phy_pause_adv_yt;
diff --git a/drivers/net/ngbe/base/ngbe_phy_mvl.c b/drivers/net/ngbe/base/ngbe_phy_mvl.c
index a828597e7b..85af6bc99c 100644
--- a/drivers/net/ngbe/base/ngbe_phy_mvl.c
+++ b/drivers/net/ngbe/base/ngbe_phy_mvl.c
@@ -121,9 +121,7 @@ s32 ngbe_init_phy_mvl(struct ngbe_hw *hw)
 	value = MVL_INTR_EN_ANC | MVL_INTR_EN_LSC;
 	hw->phy.write_reg(hw, MVL_INTR_EN, 0, value);
 
-	ngbe_read_phy_reg_mdi(hw, MVL_CTRL, 0, &value);
-	value |= MVL_CTRL_PWDN;
-	ngbe_write_phy_reg_mdi(hw, MVL_CTRL, 0, value);
+	hw->phy.set_phy_power(hw, false);
 
 	return ret_val;
 }
@@ -205,7 +203,7 @@ s32 ngbe_setup_phy_link_mvl(struct ngbe_hw *hw, u32 speed,
 		value_r9 |= value;
 		hw->phy.write_reg(hw, MVL_PHY_1000BASET, 0, value_r9);
 	} else {
-		hw->phy.autoneg_advertised = 1;
+		hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL;
 
 		hw->phy.read_reg(hw, MVL_ANA, 0, &value);
 		value &= ~(MVL_PHY_1000BASEX_HALF | MVL_PHY_1000BASEX_FULL);
@@ -217,9 +215,7 @@ s32 ngbe_setup_phy_link_mvl(struct ngbe_hw *hw, u32 speed,
 	ngbe_write_phy_reg_mdi(hw, MVL_CTRL, 0, value);
 
 skip_an:
-	ngbe_read_phy_reg_mdi(hw, MVL_CTRL, 0, &value);
-	value |= MVL_CTRL_PWDN;
-	ngbe_write_phy_reg_mdi(hw, MVL_CTRL, 0, value);
+	hw->phy.set_phy_power(hw, true);
 
 	hw->phy.read_reg(hw, MVL_INTR, 0, &value);
 
@@ -356,3 +352,16 @@ s32 ngbe_check_phy_link_mvl(struct ngbe_hw *hw,
 	return status;
 }
 
+s32 ngbe_set_phy_power_mvl(struct ngbe_hw *hw, bool on)
+{
+	u16 value = 0;
+
+	hw->phy.read_reg(hw, MVL_CTRL, 0, &value);
+	if (on)
+		value &= ~MVL_CTRL_PWDN;
+	else
+		value |= MVL_CTRL_PWDN;
+	hw->phy.write_reg(hw, MVL_CTRL, 0, value);
+
+	return 0;
+}
diff --git a/drivers/net/ngbe/base/ngbe_phy_mvl.h b/drivers/net/ngbe/base/ngbe_phy_mvl.h
index 8aee236390..ab07c99fe4 100644
--- a/drivers/net/ngbe/base/ngbe_phy_mvl.h
+++ b/drivers/net/ngbe/base/ngbe_phy_mvl.h
@@ -97,6 +97,7 @@ s32 ngbe_reset_phy_mvl(struct ngbe_hw *hw);
 
 s32 ngbe_check_phy_link_mvl(struct ngbe_hw *hw,
 		u32 *speed, bool *link_up);
+s32 ngbe_set_phy_power_mvl(struct ngbe_hw *hw, bool on);
 s32 ngbe_setup_phy_link_mvl(struct ngbe_hw *hw,
 			u32 speed, bool autoneg_wait_to_complete);
 s32 ngbe_get_phy_advertised_pause_mvl(struct ngbe_hw *hw, u8 *pause_bit);
diff --git a/drivers/net/ngbe/base/ngbe_phy_yt.c b/drivers/net/ngbe/base/ngbe_phy_yt.c
index 34d69707dd..f46121b8d1 100644
--- a/drivers/net/ngbe/base/ngbe_phy_yt.c
+++ b/drivers/net/ngbe/base/ngbe_phy_yt.c
@@ -100,23 +100,13 @@ s32 ngbe_write_phy_reg_sds_ext_yt(struct ngbe_hw *hw,
 
 s32 ngbe_init_phy_yt(struct ngbe_hw *hw)
 {
-	u16 value = 0;
-
 	/* close sds area register */
 	ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY, 0, 0);
 	/* enable interrupts */
 	ngbe_write_phy_reg_mdi(hw, YT_INTR, 0,
 				YT_INTR_ENA_MASK | YT_SDS_INTR_ENA_MASK);
 
-	/* power down in fiber mode */
-	hw->phy.read_reg(hw, YT_BCR, 0, &value);
-	value |= YT_BCR_PWDN;
-	hw->phy.write_reg(hw, YT_BCR, 0, value);
-
-	/* power down in UTP mode */
-	ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value);
-	value |= YT_BCR_PWDN;
-	ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value);
+	hw->phy.set_phy_power(hw, false);
 
 	return 0;
 }
@@ -200,10 +190,7 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,
 		value |= YT_BCR_RESET | YT_BCR_ANE | YT_BCR_RESTART_AN;
 		hw->phy.write_reg(hw, YT_BCR, 0, value);
 skip_an:
-		/* power on in UTP mode */
-		ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value);
-		value &= ~YT_BCR_PWDN;
-		ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value);
+		hw->phy.set_phy_power(hw, true);
 	} else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(1)) {
 		/* fiber to rgmii */
 		hw->phy.autoneg_advertised |= NGBE_LINK_SPEED_1GB_FULL;
@@ -221,19 +208,9 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,
 		/* software reset */
 		ngbe_write_phy_reg_sds_ext_yt(hw, 0x0, 0, 0x9140);
 
-		/* power on phy */
-		hw->phy.read_reg(hw, YT_BCR, 0, &value);
-		value &= ~YT_BCR_PWDN;
-		hw->phy.write_reg(hw, YT_BCR, 0, value);
+		hw->phy.set_phy_power(hw, true);
 	} else if ((value & YT_CHIP_MODE_MASK) == YT_CHIP_MODE_SEL(2)) {
-		/* power on in UTP mode */
-		ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value);
-		value &= ~YT_BCR_PWDN;
-		ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value);
-		/* power down in fiber mode */
-		hw->phy.read_reg(hw, YT_BCR, 0, &value);
-		value &= ~YT_BCR_PWDN;
-		hw->phy.write_reg(hw, YT_BCR, 0, value);
+		hw->phy.set_phy_power(hw, true);
 
 		hw->phy.read_reg(hw, YT_SPST, 0, &value);
 		if (value & YT_SPST_LINK) {
@@ -303,10 +280,7 @@ s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw, u32 speed,
 		value &= ~YT_SMI_PHY_SW_RST;
 		ngbe_write_phy_reg_ext_yt(hw, YT_CHIP, 0, value);
 
-		/* power on phy */
-		hw->phy.read_reg(hw, YT_BCR, 0, &value);
-		value &= ~YT_BCR_PWDN;
-		hw->phy.write_reg(hw, YT_BCR, 0, value);
+		hw->phy.set_phy_power(hw, true);
 	}
 
 	ngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY, 0, 0);
@@ -434,3 +408,26 @@ s32 ngbe_check_phy_link_yt(struct ngbe_hw *hw,
 	return status;
 }
 
+s32 ngbe_set_phy_power_yt(struct ngbe_hw *hw, bool on)
+{
+	u16 value = 0;
+
+	/* power down/up in fiber mode */
+	hw->phy.read_reg(hw, YT_BCR, 0, &value);
+	if (on)
+		value &= ~YT_BCR_PWDN;
+	else
+		value |= YT_BCR_PWDN;
+	hw->phy.write_reg(hw, YT_BCR, 0, value);
+
+	value = 0;
+	/* power down/up in UTP mode */
+	ngbe_read_phy_reg_mdi(hw, YT_BCR, 0, &value);
+	if (on)
+		value &= ~YT_BCR_PWDN;
+	else
+		value |= YT_BCR_PWDN;
+	ngbe_write_phy_reg_mdi(hw, YT_BCR, 0, value);
+
+	return 0;
+}
diff --git a/drivers/net/ngbe/base/ngbe_phy_yt.h b/drivers/net/ngbe/base/ngbe_phy_yt.h
index dca5174e4e..06e8f77261 100644
--- a/drivers/net/ngbe/base/ngbe_phy_yt.h
+++ b/drivers/net/ngbe/base/ngbe_phy_yt.h
@@ -89,6 +89,8 @@ s32 ngbe_reset_phy_yt(struct ngbe_hw *hw);
 
 s32 ngbe_check_phy_link_yt(struct ngbe_hw *hw,
 		u32 *speed, bool *link_up);
+s32 ngbe_set_phy_power_yt(struct ngbe_hw *hw, bool on);
+
 s32 ngbe_setup_phy_link_yt(struct ngbe_hw *hw,
 			u32 speed, bool autoneg_wait_to_complete);
 s32 ngbe_get_phy_advertised_pause_yt(struct ngbe_hw *hw,
diff --git a/drivers/net/ngbe/ngbe_ethdev.c b/drivers/net/ngbe/ngbe_ethdev.c
index c7301a9616..9df9f824a1 100644
--- a/drivers/net/ngbe/ngbe_ethdev.c
+++ b/drivers/net/ngbe/ngbe_ethdev.c
@@ -1165,6 +1165,8 @@ ngbe_dev_stop(struct rte_eth_dev *dev)
 	for (vf = 0; vfinfo != NULL && vf < pci_dev->max_vfs; vf++)
 		vfinfo[vf].clear_to_send = false;
 
+	hw->phy.set_phy_power(hw, false);
+
 	ngbe_dev_clear_queues(dev);
 
 	/* Clear stored conf */
@@ -1874,16 +1876,8 @@ ngbe_dev_link_update_share(struct rte_eth_dev *dev,
 		return rte_eth_linkstatus_set(dev, &link);
 	}
 
-	if (!link_up) {
-		if (hw->phy.media_type == ngbe_media_type_fiber &&
-			hw->phy.type != ngbe_phy_mvl_sfi) {
-			intr->flags |= NGBE_FLAG_NEED_LINK_CONFIG;
-			rte_eal_alarm_set(10,
-				ngbe_dev_setup_link_alarm_handler, dev);
-		}
-
+	if (!link_up)
 		return rte_eth_linkstatus_set(dev, &link);
-	}
 
 	intr->flags &= ~NGBE_FLAG_NEED_LINK_CONFIG;
 	link.link_status = RTE_ETH_LINK_UP;
-- 
2.27.0

[PATCH 5/9] net/ngbe: fix to read M88E1512 PHY mode

[Jiawen Wu]

For M88E1512 PHY mixed mode, PXE driver overrides PHY mode at load
time. To workaround this problem, change to read PHY mode from flash
instead of register.

Fixes: 1c44384fce76 ("net/ngbe: support custom PHY interfaces")
Cc: stable@dpdk.org

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
---
 drivers/net/ngbe/base/ngbe_hw.c      | 37 ++++++++++++++++++++++++++++
 drivers/net/ngbe/base/ngbe_hw.h      |  3 +++
 drivers/net/ngbe/base/ngbe_phy_mvl.c |  9 ++++---
 drivers/net/ngbe/base/ngbe_phy_mvl.h |  1 +
 4 files changed, 46 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ngbe/base/ngbe_hw.c b/drivers/net/ngbe/base/ngbe_hw.c
index fa2d749240..050649e0a6 100644
--- a/drivers/net/ngbe/base/ngbe_hw.c
+++ b/drivers/net/ngbe/base/ngbe_hw.c
@@ -1805,6 +1805,43 @@ s32 ngbe_enable_rx_dma(struct ngbe_hw *hw, u32 regval)
 	return 0;
 }
 
+/* cmd_addr is used for some special command:
+ * 1. to be sector address, when implemented erase sector command
+ * 2. to be flash address when implemented read, write flash address
+ */
+u32 ngbe_fmgr_cmd_op(struct ngbe_hw *hw, u32 cmd, u32 cmd_addr)
+{
+	u32 cmd_val = 0;
+	u32 i = 0;
+
+	cmd_val = NGBE_SPICMD_CMD(cmd) | NGBE_SPICMD_CLK(3) | cmd_addr;
+	wr32(hw, NGBE_SPICMD, cmd_val);
+
+	for (i = 0; i < 10000; i++) {
+		if (rd32(hw, NGBE_SPISTAT) & NGBE_SPISTAT_OPDONE)
+			break;
+
+		usec_delay(10);
+	}
+	if (i == 10000)
+		return 1;
+
+	return 0;
+}
+
+u32 ngbe_flash_read_dword(struct ngbe_hw *hw, u32 addr)
+{
+	u32 status = 0;
+
+	status = ngbe_fmgr_cmd_op(hw, 1, addr);
+	if (status) {
+		DEBUGOUT("Read flash timeout.");
+		return status;
+	}
+
+	return rd32(hw, NGBE_SPIDAT);
+}
+
 void ngbe_map_device_id(struct ngbe_hw *hw)
 {
 	u16 oem = hw->sub_system_id & NGBE_OEM_MASK;
diff --git a/drivers/net/ngbe/base/ngbe_hw.h b/drivers/net/ngbe/base/ngbe_hw.h
index 7e0e23b195..2813e72d60 100644
--- a/drivers/net/ngbe/base/ngbe_hw.h
+++ b/drivers/net/ngbe/base/ngbe_hw.h
@@ -83,4 +83,7 @@ s32 ngbe_init_phy(struct ngbe_hw *hw);
 s32 ngbe_enable_rx_dma(struct ngbe_hw *hw, u32 regval);
 void ngbe_map_device_id(struct ngbe_hw *hw);
 
+u32 ngbe_fmgr_cmd_op(struct ngbe_hw *hw, u32 cmd, u32 cmd_addr);
+u32 ngbe_flash_read_dword(struct ngbe_hw *hw, u32 addr);
+
 #endif /* _NGBE_HW_H_ */
diff --git a/drivers/net/ngbe/base/ngbe_phy_mvl.c b/drivers/net/ngbe/base/ngbe_phy_mvl.c
index 85af6bc99c..c5256359ed 100644
--- a/drivers/net/ngbe/base/ngbe_phy_mvl.c
+++ b/drivers/net/ngbe/base/ngbe_phy_mvl.c
@@ -50,11 +50,12 @@ s32 ngbe_write_phy_reg_mvl(struct ngbe_hw *hw,
 
 s32 ngbe_check_phy_mode_mvl(struct ngbe_hw *hw)
 {
-	u16 value = 0;
+	u8 value = 0;
+	u32 phy_mode = 0;
+
+	phy_mode = ngbe_flash_read_dword(hw, 0xFF010);
+	value = (u8)(phy_mode >> (hw->bus.lan_id * 8));
 
-	/* select page 18 reg 20 */
-	ngbe_write_phy_reg_mdi(hw, MVL_PAGE_SEL, 0, 18);
-	ngbe_read_phy_reg_mdi(hw, MVL_GEN_CTL, 0, &value);
 	if (MVL_GEN_CTL_MODE(value) == MVL_GEN_CTL_MODE_COPPER) {
 		/* mode select to RGMII-to-copper */
 		hw->phy.type = ngbe_phy_mvl;
diff --git a/drivers/net/ngbe/base/ngbe_phy_mvl.h b/drivers/net/ngbe/base/ngbe_phy_mvl.h
index ab07c99fe4..1cf49ac8c5 100644
--- a/drivers/net/ngbe/base/ngbe_phy_mvl.h
+++ b/drivers/net/ngbe/base/ngbe_phy_mvl.h
@@ -3,6 +3,7 @@
  */
 
 #include "ngbe_phy.h"
+#include "ngbe_hw.h"
 
 #ifndef _NGBE_PHY_MVL_H_
 #define _NGBE_PHY_MVL_H_
-- 
2.27.0

[PATCH 6/9] net/ngbe: change PCIe related operations to use rte API

[Jiawen Wu]

When using mailbox to request firmware to enable or disable PCIe bus
master, there is a small probability that mailbox cannot respond.
Change to use rte_pci_read_config() and rte_pci_write_config(), to
avoid this problem.

Fixes: ac6c5e9af56a ("net/ngbe: fix Tx hang on queue disable")
Cc: stable@dpdk.org

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
---
 drivers/net/ngbe/base/ngbe_hw.c    | 25 +++++++++++++++++++------
 drivers/net/ngbe/base/ngbe_osdep.h |  4 ++++
 drivers/net/ngbe/ngbe_ethdev.c     |  1 +
 3 files changed, 24 insertions(+), 6 deletions(-)

diff --git a/drivers/net/ngbe/base/ngbe_hw.c b/drivers/net/ngbe/base/ngbe_hw.c
index 050649e0a6..facc1d9e82 100644
--- a/drivers/net/ngbe/base/ngbe_hw.c
+++ b/drivers/net/ngbe/base/ngbe_hw.c
@@ -1058,17 +1058,30 @@ void ngbe_fc_autoneg(struct ngbe_hw *hw)
  **/
 s32 ngbe_set_pcie_master(struct ngbe_hw *hw, bool enable)
 {
+	struct rte_pci_device *pci_dev = (struct rte_pci_device *)hw->back;
 	s32 status = 0;
-	u16 addr = 0x04;
-	u32 data, i;
+	s32 ret = 0;
+	u32 i;
+	u16 reg;
+
+	ret = rte_pci_read_config(pci_dev, &reg,
+			sizeof(reg), PCI_COMMAND);
+	if (ret != sizeof(reg)) {
+		DEBUGOUT("Cannot read command from PCI config space!\n");
+		return -1;
+	}
 
-	ngbe_hic_pcie_read(hw, addr, &data, 4);
 	if (enable)
-		data |= 0x04;
+		reg |= PCI_COMMAND_MASTER;
 	else
-		data &= ~0x04;
+		reg &= ~PCI_COMMAND_MASTER;
 
-	ngbe_hic_pcie_write(hw, addr, &data, 4);
+	ret = rte_pci_write_config(pci_dev, &reg,
+			sizeof(reg), PCI_COMMAND);
+	if (ret != sizeof(reg)) {
+		DEBUGOUT("Cannot write command to PCI config space!\n");
+		return -1;
+	}
 
 	if (enable)
 		goto out;
diff --git a/drivers/net/ngbe/base/ngbe_osdep.h b/drivers/net/ngbe/base/ngbe_osdep.h
index b62d793191..bf1fa30312 100644
--- a/drivers/net/ngbe/base/ngbe_osdep.h
+++ b/drivers/net/ngbe/base/ngbe_osdep.h
@@ -19,6 +19,7 @@
 #include <rte_config.h>
 #include <rte_io.h>
 #include <rte_ether.h>
+#include <rte_bus_pci.h>
 
 #include "../ngbe_logs.h"
 
@@ -180,4 +181,7 @@ static inline u64 REVERT_BIT_MASK64(u64 mask)
 #define ETH_P_8021Q      0x8100
 #define ETH_P_8021AD     0x88A8
 
+#define PCI_COMMAND		0x04
+#define  PCI_COMMAND_MASTER	0x4
+
 #endif /* _NGBE_OS_H_ */
diff --git a/drivers/net/ngbe/ngbe_ethdev.c b/drivers/net/ngbe/ngbe_ethdev.c
index 9df9f824a1..5ac1c27a58 100644
--- a/drivers/net/ngbe/ngbe_ethdev.c
+++ b/drivers/net/ngbe/ngbe_ethdev.c
@@ -356,6 +356,7 @@ eth_ngbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
 	eth_dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
 
 	/* Vendor and Device ID need to be set before init of shared code */
+	hw->back = pci_dev;
 	hw->device_id = pci_dev->id.device_id;
 	hw->vendor_id = pci_dev->id.vendor_id;
 	hw->sub_system_id = pci_dev->id.subsystem_device_id;
-- 
2.27.0

[PATCH 7/9] net/ngbe: redesign internal PHY init flow

[Jiawen Wu]

Add to read efuse values from flash, and disable EEE to improve signal
quality. Remove PHY semaphore to access PHY registers faster. And remove
unnecessary page selection where quick access is required.

When rte_eth_link_get_nowait() is called frequently with LSC disabled by
self-developed applications, eventually the PHY status register will be
accessed frequently. It will cause internal PHY init failure, if they are
done simultaneously. So there is a protection added for internal PHY init.

Fixes: 3518df5774c7 ("net/ngbe: support device start/stop")
Fixes: 91bc12c5227c ("net/ngbe: optimize PHY initialization process")
Cc: stable@dpdk.org

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
---
 drivers/net/ngbe/base/ngbe_hw.c      |  16 ++++
 drivers/net/ngbe/base/ngbe_hw.h      |   1 +
 drivers/net/ngbe/base/ngbe_phy.c     |  12 ---
 drivers/net/ngbe/base/ngbe_phy_rtl.c | 106 ++++++++++++++++++++-------
 drivers/net/ngbe/base/ngbe_type.h    |   2 +
 5 files changed, 100 insertions(+), 37 deletions(-)

diff --git a/drivers/net/ngbe/base/ngbe_hw.c b/drivers/net/ngbe/base/ngbe_hw.c
index facc1d9e82..c1114ba3b1 100644
--- a/drivers/net/ngbe/base/ngbe_hw.c
+++ b/drivers/net/ngbe/base/ngbe_hw.c
@@ -53,6 +53,7 @@ s32 ngbe_init_hw(struct ngbe_hw *hw)
 {
 	s32 status;
 
+	ngbe_read_efuse(hw);
 	ngbe_save_eeprom_version(hw);
 
 	/* Reset the hardware */
@@ -1855,6 +1856,21 @@ u32 ngbe_flash_read_dword(struct ngbe_hw *hw, u32 addr)
 	return rd32(hw, NGBE_SPIDAT);
 }
 
+void ngbe_read_efuse(struct ngbe_hw *hw)
+{
+	u32 efuse[2];
+	u8 lan_id = hw->bus.lan_id;
+
+	efuse[0] = ngbe_flash_read_dword(hw, 0xfe010 + lan_id * 8);
+	efuse[1] = ngbe_flash_read_dword(hw, 0xfe010 + lan_id * 8 + 4);
+
+	DEBUGOUT("port %d efuse[0] = %08x, efuse[1] = %08x\n",
+		lan_id, efuse[0], efuse[1]);
+
+	hw->gphy_efuse[0] = efuse[0];
+	hw->gphy_efuse[1] = efuse[1];
+}
+
 void ngbe_map_device_id(struct ngbe_hw *hw)
 {
 	u16 oem = hw->sub_system_id & NGBE_OEM_MASK;
diff --git a/drivers/net/ngbe/base/ngbe_hw.h b/drivers/net/ngbe/base/ngbe_hw.h
index 2813e72d60..b92a691fa0 100644
--- a/drivers/net/ngbe/base/ngbe_hw.h
+++ b/drivers/net/ngbe/base/ngbe_hw.h
@@ -83,6 +83,7 @@ s32 ngbe_init_phy(struct ngbe_hw *hw);
 s32 ngbe_enable_rx_dma(struct ngbe_hw *hw, u32 regval);
 void ngbe_map_device_id(struct ngbe_hw *hw);
 
+void ngbe_read_efuse(struct ngbe_hw *hw);
 u32 ngbe_fmgr_cmd_op(struct ngbe_hw *hw, u32 cmd, u32 cmd_addr);
 u32 ngbe_flash_read_dword(struct ngbe_hw *hw, u32 addr);
 
diff --git a/drivers/net/ngbe/base/ngbe_phy.c b/drivers/net/ngbe/base/ngbe_phy.c
index 84f2925e7e..06562b594f 100644
--- a/drivers/net/ngbe/base/ngbe_phy.c
+++ b/drivers/net/ngbe/base/ngbe_phy.c
@@ -290,16 +290,10 @@ s32 ngbe_read_phy_reg(struct ngbe_hw *hw, u32 reg_addr,
 			       u32 device_type, u16 *phy_data)
 {
 	s32 err;
-	u32 gssr = hw->phy.phy_semaphore_mask;
-
-	if (hw->mac.acquire_swfw_sync(hw, gssr))
-		return NGBE_ERR_SWFW_SYNC;
 
 	err = hw->phy.read_reg_unlocked(hw, reg_addr, device_type,
 					phy_data);
 
-	hw->mac.release_swfw_sync(hw, gssr);
-
 	return err;
 }
 
@@ -350,16 +344,10 @@ s32 ngbe_write_phy_reg(struct ngbe_hw *hw, u32 reg_addr,
 				u32 device_type, u16 phy_data)
 {
 	s32 err;
-	u32 gssr = hw->phy.phy_semaphore_mask;
-
-	if (hw->mac.acquire_swfw_sync(hw, gssr))
-		err = NGBE_ERR_SWFW_SYNC;
 
 	err = hw->phy.write_reg_unlocked(hw, reg_addr, device_type,
 					 phy_data);
 
-	hw->mac.release_swfw_sync(hw, gssr);
-
 	return err;
 }
 
diff --git a/drivers/net/ngbe/base/ngbe_phy_rtl.c b/drivers/net/ngbe/base/ngbe_phy_rtl.c
index 3a2d624ddb..33c5e79e87 100644
--- a/drivers/net/ngbe/base/ngbe_phy_rtl.c
+++ b/drivers/net/ngbe/base/ngbe_phy_rtl.c
@@ -14,7 +14,9 @@ s32 ngbe_read_phy_reg_rtl(struct ngbe_hw *hw,
 	reg.addr = reg_addr;
 	ngbe_mdi_map_register(&reg, &reg22);
 
-	wr32(hw, NGBE_PHY_CONFIG(RTL_PAGE_SELECT), reg22.page);
+	if (!(reg22.page == 0xa43 &&
+			(reg22.addr == 0x1a || reg22.addr == 0x1d)))
+		wr32(hw, NGBE_PHY_CONFIG(RTL_PAGE_SELECT), reg22.page);
 	*phy_data = 0xFFFF & rd32(hw, NGBE_PHY_CONFIG(reg22.addr));
 
 	return 0;
@@ -30,7 +32,9 @@ s32 ngbe_write_phy_reg_rtl(struct ngbe_hw *hw,
 	reg.addr = reg_addr;
 	ngbe_mdi_map_register(&reg, &reg22);
 
-	wr32(hw, NGBE_PHY_CONFIG(RTL_PAGE_SELECT), reg22.page);
+	if (!(reg22.page == 0xa43 &&
+			(reg22.addr == 0x1a || reg22.addr == 0x1d)))
+		wr32(hw, NGBE_PHY_CONFIG(RTL_PAGE_SELECT), reg22.page);
 	wr32(hw, NGBE_PHY_CONFIG(reg22.addr), phy_data);
 
 	return 0;
@@ -60,16 +64,61 @@ static void ngbe_phy_led_ctrl_rtl(struct ngbe_hw *hw)
 	hw->phy.write_reg(hw, RTL_LPCR, 0xd04, value);
 }
 
+static s32 ngbe_wait_mdio_access_on(struct ngbe_hw *hw)
+{
+	int i;
+	u16 val = 0;
+
+	for (i = 0; i < 100; i++) {
+		/* irq status */
+		hw->phy.read_reg(hw, RTL_INSR, 0xa43, &val);
+		if (val & RTL_INSR_ACCESS)
+			break;
+		msec_delay(1);
+	}
+
+	if (i == 100) {
+		DEBUGOUT("wait_mdio_access_on timeout");
+		return NGBE_ERR_PHY_TIMEOUT;
+	}
+
+	return 0;
+}
+
+static void ngbe_efuse_calibration(struct ngbe_hw *hw)
+{
+	u32 efuse[2];
+
+	ngbe_wait_mdio_access_on(hw);
+
+	efuse[0] = hw->gphy_efuse[0];
+	efuse[1] = hw->gphy_efuse[1];
+
+	if (!efuse[0] && !efuse[1]) {
+		efuse[0] = 0xFFFFFFFF;
+		efuse[1] = 0xFFFFFFFF;
+	}
+
+	/* calibration */
+	efuse[0] |= 0xF0000100;
+	efuse[1] |= 0xFF807FFF;
+	DEBUGOUT("port %d efuse[0] = %08x, efuse[1] = %08x",
+		hw->bus.lan_id, efuse[0], efuse[1]);
+
+	/* EODR, Efuse Output Data Register */
+	hw->phy.write_reg(hw, 16, 0xa46, (efuse[0] >>  0) & 0xFFFF);
+	hw->phy.write_reg(hw, 17, 0xa46, (efuse[0] >> 16) & 0xFFFF);
+	hw->phy.write_reg(hw, 18, 0xa46, (efuse[1] >>  0) & 0xFFFF);
+	hw->phy.write_reg(hw, 19, 0xa46, (efuse[1] >> 16) & 0xFFFF);
+}
+
 s32 ngbe_init_phy_rtl(struct ngbe_hw *hw)
 {
 	int i;
 	u16 value = 0;
 
-	/* enable interrupts, only link status change and an done is allowed */
-	value = RTL_INER_LSC | RTL_INER_ANC;
-	hw->phy.write_reg(hw, RTL_INER, 0xa42, value);
-
-	hw->phy.read_reg(hw, RTL_INSR, 0xa43, &value);
+	hw->init_phy = true;
+	msec_delay(1);
 
 	for (i = 0; i < 15; i++) {
 		if (!rd32m(hw, NGBE_STAT,
@@ -83,6 +132,8 @@ s32 ngbe_init_phy_rtl(struct ngbe_hw *hw)
 		return NGBE_ERR_PHY_TIMEOUT;
 	}
 
+	ngbe_efuse_calibration(hw);
+
 	hw->phy.write_reg(hw, RTL_SCR, 0xa46, RTL_SCR_EFUSE);
 	hw->phy.read_reg(hw, RTL_SCR, 0xa46, &value);
 	if (!(value & RTL_SCR_EFUSE)) {
@@ -90,15 +141,10 @@ s32 ngbe_init_phy_rtl(struct ngbe_hw *hw)
 		return NGBE_ERR_PHY_TIMEOUT;
 	}
 
-	for (i = 0; i < 1000; i++) {
-		hw->phy.read_reg(hw, RTL_INSR, 0xa43, &value);
-		if (value & RTL_INSR_ACCESS)
-			break;
-		msec_delay(1);
-	}
-	if (i == 1000)
-		DEBUGOUT("PHY wait mdio 1 access timeout.");
+	ngbe_wait_mdio_access_on(hw);
 
+	hw->phy.write_reg(hw, 27, 0xa42, 0x8011);
+	hw->phy.write_reg(hw, 28, 0xa42, 0x5737);
 
 	hw->phy.write_reg(hw, RTL_SCR, 0xa46, RTL_SCR_EXTINI);
 	hw->phy.read_reg(hw, RTL_SCR, 0xa46, &value);
@@ -107,24 +153,26 @@ s32 ngbe_init_phy_rtl(struct ngbe_hw *hw)
 		return NGBE_ERR_PHY_TIMEOUT;
 	}
 
-	for (i = 0; i < 1000; i++) {
-		hw->phy.read_reg(hw, RTL_INSR, 0xa43, &value);
-		if (value & RTL_INSR_ACCESS)
-			break;
-		msec_delay(1);
-	}
-	if (i == 1000)
-		DEBUGOUT("PHY wait mdio 2 access timeout.");
+	ngbe_wait_mdio_access_on(hw);
 
-	for (i = 0; i < 1000; i++) {
+	for (i = 0; i < 100; i++) {
 		hw->phy.read_reg(hw, RTL_GSR, 0xa42, &value);
 		if ((value & RTL_GSR_ST) == RTL_GSR_ST_LANON)
 			break;
 		msec_delay(1);
 	}
-	if (i == 1000)
+	if (i == 100)
 		return NGBE_ERR_PHY_TIMEOUT;
 
+	/* Disable EEE */
+	hw->phy.write_reg(hw, 0x11, 0xa4b, 0x1110);
+	hw->phy.write_reg(hw, 0xd, 0x0, 0x0007);
+	hw->phy.write_reg(hw, 0xe, 0x0, 0x003c);
+	hw->phy.write_reg(hw, 0xd, 0x0, 0x4007);
+	hw->phy.write_reg(hw, 0xe, 0x0, 0x0000);
+
+	hw->init_phy = false;
+
 	return 0;
 }
 
@@ -142,6 +190,9 @@ s32 ngbe_setup_phy_link_rtl(struct ngbe_hw *hw,
 
 	UNREFERENCED_PARAMETER(autoneg_wait_to_complete);
 
+	hw->init_phy = true;
+	msec_delay(1);
+
 	hw->phy.read_reg(hw, RTL_INSR, 0xa43, &autoneg_reg);
 
 	if (!hw->mac.autoneg) {
@@ -243,6 +294,8 @@ s32 ngbe_setup_phy_link_rtl(struct ngbe_hw *hw,
 skip_an:
 	ngbe_phy_led_ctrl_rtl(hw);
 
+	hw->init_phy = false;
+
 	return 0;
 }
 
@@ -309,6 +362,9 @@ s32 ngbe_check_phy_link_rtl(struct ngbe_hw *hw, u32 *speed, bool *link_up)
 	u16 phy_data = 0;
 	u16 insr = 0;
 
+	if (hw->init_phy)
+		return -1;
+
 	hw->phy.read_reg(hw, RTL_INSR, 0xa43, &insr);
 
 	/* Initialize speed and link to default case */
diff --git a/drivers/net/ngbe/base/ngbe_type.h b/drivers/net/ngbe/base/ngbe_type.h
index 666562bf22..0ad4766d2a 100644
--- a/drivers/net/ngbe/base/ngbe_type.h
+++ b/drivers/net/ngbe/base/ngbe_type.h
@@ -428,10 +428,12 @@ struct ngbe_hw {
 
 	u32 q_rx_regs[8 * 4];
 	u32 q_tx_regs[8 * 4];
+	u32 gphy_efuse[2];
 	bool offset_loaded;
 	bool is_pf;
 	bool gpio_ctl;
 	u32 led_conf;
+	bool init_phy;
 	struct {
 		u64 rx_qp_packets;
 		u64 tx_qp_packets;
-- 
2.27.0

[PATCH 8/9] net/txgbe: fix SGMII mode to link up

[Jiawen Wu]

Fix SGMII mode to link up.

Fixes: 01c3cf5c85a7 ("net/txgbe: add autoneg control read and write")
Cc: stable@dpdk.org

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
---
 drivers/net/txgbe/base/txgbe_phy.c | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/drivers/net/txgbe/base/txgbe_phy.c b/drivers/net/txgbe/base/txgbe_phy.c
index da2bbc43e0..9f46d5bdb0 100644
--- a/drivers/net/txgbe/base/txgbe_phy.c
+++ b/drivers/net/txgbe/base/txgbe_phy.c
@@ -1367,9 +1367,17 @@ static void
 txgbe_set_sgmii_an37_ability(struct txgbe_hw *hw)
 {
 	u32 value;
+	u8 device_type = hw->subsystem_device_id & 0xF0;
 
 	wr32_epcs(hw, VR_XS_OR_PCS_MMD_DIGI_CTL1, 0x3002);
-	wr32_epcs(hw, SR_MII_MMD_AN_CTL, 0x0105);
+	/* for sgmii + external phy, set to 0x0105 (phy sgmii mode) */
+	/* for sgmii direct link, set to 0x010c (mac sgmii mode) */
+	if (device_type == TXGBE_DEV_ID_MAC_SGMII ||
+			hw->phy.media_type == txgbe_media_type_fiber)
+		wr32_epcs(hw, SR_MII_MMD_AN_CTL, 0x010C);
+	else if (device_type == TXGBE_DEV_ID_SGMII ||
+			device_type == TXGBE_DEV_ID_XAUI)
+		wr32_epcs(hw, SR_MII_MMD_AN_CTL, 0x0105);
 	wr32_epcs(hw, SR_MII_MMD_DIGI_CTL, 0x0200);
 	value = rd32_epcs(hw, SR_MII_MMD_CTL);
 	value = (value & ~0x1200) | (0x1 << 12) | (0x1 << 9);
@@ -2280,6 +2288,8 @@ void txgbe_autoc_write(struct txgbe_hw *hw, u64 autoc)
 		}
 	} else if (hw->phy.media_type == txgbe_media_type_fiber) {
 		txgbe_set_link_to_sfi(hw, speed);
+		if (speed == TXGBE_LINK_SPEED_1GB_FULL)
+			txgbe_set_sgmii_an37_ability(hw);
 	}
 
 	if (speed == TXGBE_LINK_SPEED_10GB_FULL)
-- 
2.27.0

[PATCH 9/9] net/txgbe: fix max number of queues for SRIOV

[Jiawen Wu]

Hardware restrictions require a maximum of 4 queues for every pool.

Fixes: a6712cd029a4 ("net/txgbe: add PF module init and uninit for SRIOV")
Cc: stable@dpdk.org

Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
---
 drivers/net/txgbe/txgbe_pf.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/txgbe/txgbe_pf.c b/drivers/net/txgbe/txgbe_pf.c
index 67d92bfa56..0b82fb1a88 100644
--- a/drivers/net/txgbe/txgbe_pf.c
+++ b/drivers/net/txgbe/txgbe_pf.c
@@ -108,7 +108,7 @@ int txgbe_pf_host_init(struct rte_eth_dev *eth_dev)
 		nb_queue = 4;
 		RTE_ETH_DEV_SRIOV(eth_dev).active = RTE_ETH_32_POOLS;
 	} else {
-		nb_queue = 8;
+		nb_queue = 4;
 		RTE_ETH_DEV_SRIOV(eth_dev).active = RTE_ETH_16_POOLS;
 	}
 
-- 
2.27.0