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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 12.22.5.234 as permitted sender) receiver=protection.outlook.com; client-ip=12.22.5.234; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (12.22.5.234) by DM6NAM11FT027.mail.protection.outlook.com (10.13.172.205) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.5332.12 via Frontend Transport; Thu, 16 Jun 2022 08:43:41 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by DRHQMAIL101.nvidia.com (10.27.9.10) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Thu, 16 Jun 2022 08:43:41 +0000 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.22; Thu, 16 Jun 2022 01:43:33 -0700 From: Gregory Etelson To: CC: , , , , Viacheslav Ovsiienko Subject: [PATCH v2] doc: fix mlx5 flow integrity hardware support Date: Thu, 16 Jun 2022 11:43:14 +0300 Message-ID: <20220616084314.6464-1-getelson@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220616075215.4622-1-getelson@nvidia.com> References: <20220616075215.4622-1-getelson@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f74b6849-7495-44c9-2ef6-08da4f7450f9 X-MS-TrafficTypeDiagnostic: MN2PR12MB4536:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Jun 2022 08:43:41.8404 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f74b6849-7495-44c9-2ef6-08da4f7450f9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[12.22.5.234]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT027.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4536 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Current MLX5 PMD documentation stays that entire `ConnentX-6` family supports flow integrity feature. Flow integrity offload is not supported on vanilla `ConnectX-6`. It is available on `ConnectX-6 DX`, `ConnectX-6 LX` and `BlueField-2`. Cc: stable@dpdk.org Fixes: 79f8952783d0 ("net/mlx5: support integrity flow item") Signed-off-by: Gregory Etelson Acked-by: Viacheslav Ovsiienko --- v2: Update Mellanox hardware types that support integrity bits. --- doc/guides/nics/mlx5.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst index f41703277e..978886ad88 100644 --- a/doc/guides/nics/mlx5.rst +++ b/doc/guides/nics/mlx5.rst @@ -458,7 +458,7 @@ Limitations - Integrity: - - Integrity offload is enabled for **ConnectX-6** family. + - Integrity offload is enabled starting from **ConnectX-6 DX**. - Verification bits provided by the hardware are ``l3_ok``, ``ipv4_csum_ok``, ``l4_ok``, ``l4_csum_ok``. - ``level`` value 0 references outer headers. - Multiple integrity items not supported in a single flow rule. -- 2.34.1