From: Shun Hao <shunh@nvidia.com>
To: <viacheslavo@nvidia.com>, <matan@nvidia.com>, <orika@nvidia.com>,
"Xueming Li" <xuemingl@nvidia.com>
Cc: <dev@dpdk.org>, <rasland@nvidia.com>, <stable@dpdk.org>
Subject: [PATCH v1 1/2] net/mlx5: add limitation for E-Switch Manager match
Date: Sun, 19 Jun 2022 06:21:27 +0300 [thread overview]
Message-ID: <20220619032128.24588-2-shunh@nvidia.com> (raw)
In-Reply-To: <20220619032128.24588-1-shunh@nvidia.com>
For BF with old FW which doesn't expose the E-Switch Manager vport ID,
E-Switch Manager port matching works correctly only when BF is in
embedded CPU mode.
This patch adds the limitation description.
Fixes: a564038699f9 ("net/mlx5: support E-Switch manager egress traffic match")
Cc: stable@dpdk.org
Signed-off-by: Shun Hao <shunh@nvidia.com>
Acked-by: Matan Azard <matan@nvidia.com>
---
doc/guides/nics/mlx5.rst | 4 ++++
drivers/net/mlx5/mlx5_flow.h | 4 ++++
drivers/net/mlx5/mlx5_flow_dv.c | 10 ++++++++--
3 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 1b66b2bc33..f10e112d27 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -534,6 +534,10 @@ Limitations
- When configuring host shaper with MLX5_HOST_SHAPER_FLAG_AVAIL_THRESH_TRIGGERED flag set,
only rates 0 and 100Mbps are supported.
+- E-Switch Manager matching:
+
+ - For Bluefield with old FW which doesn't expose the E-Switch Manager vport ID in the capability, matching E-Switch Manager should be used only in Bluefield embedded CPU mode.
+
Statistics
----------
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index f00c033fc5..7300390070 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -2076,4 +2076,8 @@ int flow_dv_action_query(struct rte_eth_dev *dev,
size_t flow_dv_get_item_hdr_len(const enum rte_flow_item_type item_type);
int flow_dv_convert_encap_data(const struct rte_flow_item *items, uint8_t *buf,
size_t *size, struct rte_flow_error *error);
+
+#define MLX5_PF_VPORT_ID 0
+#define MLX5_ECPF_VPORT_ID 0xFFFE
+
#endif /* RTE_PMD_MLX5_FLOW_H_ */
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 65b02b20ce..09f662bdcf 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -99,6 +99,7 @@ flow_dv_get_esw_manager_vport_id(struct rte_eth_dev *dev)
struct mlx5_priv *priv = dev->data->dev_private;
struct mlx5_common_device *cdev = priv->sh->cdev;
+ /* New FW exposes E-Switch Manager vport ID, can use it directly. */
if (cdev->config.hca_attr.esw_mgr_vport_id_valid)
return (int16_t)cdev->config.hca_attr.esw_mgr_vport_id;
@@ -108,9 +109,14 @@ flow_dv_get_esw_manager_vport_id(struct rte_eth_dev *dev)
case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF:
case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF:
case PCI_DEVICE_ID_MELLANOX_CONNECTX7BF:
- return (int16_t)0xfffe;
+ /*
+ * In old FW which doesn't expose the E-Switch Manager vport ID in the capability,
+ * only the BF embedded CPUs control the E-Switch Manager port. Hence,
+ * ECPF vport ID is selected and not the host port (0) in any BF case.
+ */
+ return (int16_t)MLX5_ECPF_VPORT_ID;
default:
- return 0;
+ return MLX5_PF_VPORT_ID;
}
}
--
2.20.0
next parent reply other threads:[~2022-06-19 3:21 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20220619032128.24588-1-shunh@nvidia.com>
2022-06-19 3:21 ` Shun Hao [this message]
2022-06-19 3:21 ` [PATCH v1 2/2] net/mlx5: fix meter fail when used on E-Switch Manager Shun Hao
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