From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 21EA1A054D for ; Wed, 16 Nov 2022 21:53:15 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 7BB3042D1A; Wed, 16 Nov 2022 21:53:14 +0100 (CET) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id 8A57F40E03 for ; Wed, 16 Nov 2022 21:53:13 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668631993; x=1700167993; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=K/1lgFygdo7fXjV2UwxCgh3s4z6FDQlpNTnG6bGyMKU=; b=gF1qiz+y44UNbQ8z8cdd/XdCsKMaD1WY/yTq+GYwvRNLbZaDBJt0QUd4 wCQMJ1XaAbphE8lZ5XQBsjqJZOCLvomXI5g0/oP+24QL218lyuzsuxVAJ 5GVrARe7VwO+HDuyx2W6XlP13HkwS/fANbSBtxt9HhMdp46QmAQVfdWTb HPF7tC4F1rIfCU0cVnf/e6KqTA4dUK3yd+xiII9VqzZP0Rv+rfkmtA8N4 fCOm9dekLuxl5HPMVsDNl3UoonLJQfv6FWYVV730r6Dm+WTKx9i7G5dD4 bVWpPcbcgQ/h4IXwpKk12/q1xhwnxrFwHDNRZNvh+6Va3sJz8v8KDxfyI w==; X-IronPort-AV: E=McAfee;i="6500,9779,10533"; a="398946780" X-IronPort-AV: E=Sophos;i="5.96,169,1665471600"; d="scan'208";a="398946780" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2022 12:51:43 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10533"; a="590334503" X-IronPort-AV: E=Sophos;i="5.96,169,1665471600"; d="scan'208";a="590334503" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga003.jf.intel.com with ESMTP; 16 Nov 2022 12:51:43 -0800 From: Hernan Vargas To: stable@dpdk.org, ktraynor@redhat.com Cc: nicolas.chautru@intel.com, Hernan Vargas , Maxime Coquelin Subject: [PATCH 21.11 2/7] baseband/acc100: check AQ availability Date: Wed, 16 Nov 2022 20:46:47 -0800 Message-Id: <20221117044652.163000-3-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221117044652.163000-1-hernan.vargas@intel.com> References: <20221117044652.163000-1-hernan.vargas@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org [ upstream commit 2df5fe2023c9c7e4a858960f70c7a3b849be1bc1 ] In some corner case to run more batch enqueue than supported. A protection is required to avoid that corner case. Enhance all ACC100 enqueue operations with check to see if there is room in the atomic queue(AQ) for enqueueing batches into the queue manager. Fixes: 5ad5060f8f7 ("baseband/acc100: add LDPC processing functions") Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc100/rte_acc100_pmd.c | 31 ++++++++++++++++++------ 1 file changed, 24 insertions(+), 7 deletions(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index 254f256c80..d13f574b46 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -3464,12 +3464,27 @@ acc100_enqueue_enc_tb(struct rte_bbdev_queue_data *q_data, return i; } +/* Check room in AQ for the enqueues batches into Qmgr */ +static inline int32_t +acc100_aq_avail(struct rte_bbdev_queue_data *q_data, uint16_t num_ops) +{ + struct acc100_queue *q = q_data->queue_private; + int32_t aq_avail = q->aq_depth - + ((q->aq_enqueued - q->aq_dequeued + + ACC100_MAX_QUEUE_DEPTH) % ACC100_MAX_QUEUE_DEPTH) + - (num_ops >> 7); + + return aq_avail; +} + /* Enqueue encode operations for ACC100 device. */ static uint16_t acc100_enqueue_enc(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_enc_op **ops, uint16_t num) { - if (unlikely(num == 0)) + int32_t aq_avail = acc100_aq_avail(q_data, num); + + if (unlikely((aq_avail <= 0) || (num == 0))) return 0; if (ops[0]->turbo_enc.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) return acc100_enqueue_enc_tb(q_data, ops, num); @@ -3482,7 +3497,9 @@ static uint16_t acc100_enqueue_ldpc_enc(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_enc_op **ops, uint16_t num) { - if (unlikely(num == 0)) + int32_t aq_avail = acc100_aq_avail(q_data, num); + + if (unlikely((aq_avail <= 0) || (num == 0))) return 0; if (ops[0]->ldpc_enc.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) return acc100_enqueue_enc_tb(q_data, ops, num); @@ -3667,7 +3684,9 @@ static uint16_t acc100_enqueue_dec(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_dec_op **ops, uint16_t num) { - if (unlikely(num == 0)) + int32_t aq_avail = acc100_aq_avail(q_data, num); + + if (unlikely((aq_avail <= 0) || (num == 0))) return 0; if (ops[0]->turbo_dec.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) return acc100_enqueue_dec_tb(q_data, ops, num); @@ -3680,11 +3699,9 @@ static uint16_t acc100_enqueue_ldpc_dec(struct rte_bbdev_queue_data *q_data, struct rte_bbdev_dec_op **ops, uint16_t num) { - struct acc100_queue *q = q_data->queue_private; - int32_t aq_avail = q->aq_depth + - (q->aq_dequeued - q->aq_enqueued) / 128; + int32_t aq_avail = acc100_aq_avail(q_data, num); - if (unlikely((aq_avail == 0) || (num == 0))) + if (unlikely((aq_avail <= 0) || (num == 0))) return 0; if (ops[0]->ldpc_dec.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) -- 2.37.1