From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 28021A054D for ; Wed, 16 Nov 2022 21:53:16 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id BC69142D21; Wed, 16 Nov 2022 21:53:15 +0100 (CET) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mails.dpdk.org (Postfix) with ESMTP id 517A340F18 for ; Wed, 16 Nov 2022 21:53:14 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668631994; x=1700167994; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=GcIicCtQKfXp7mvEByZcyheekTm7gaPTcSTW7q63PiY=; b=IKZmpGseZCHJ6u6fK6WqWbM0DBQlicKxJh3rcFNtRCKxcjq59X4LCveL 2awseDEkyacV36us/UG50yr+KS0hYUBbPvLQnWRA2xMldZINo9wuiL3eE V3iy+J2HIAzv1wb1ilOwdaezk6Y+0xuqTVv73aA9tgrg8wYETP4+N2Wxh BVB3yePN7wns1uEk0MAuFPrLs2fsaKNYTzb/s1P3sW77IBKQEcj05Nz9w s2+64E/8qm9QN81LKYBmvpDUte8HGFLdZ9bbYUFNTKJg9T3VmMYaNqY0k QTDuYp5xCukK0umc4ehzjqKqoxw/TnCA+S8LBQPLt9ADTDedbW/BT4RsF g==; X-IronPort-AV: E=McAfee;i="6500,9779,10533"; a="398946797" X-IronPort-AV: E=Sophos;i="5.96,169,1665471600"; d="scan'208";a="398946797" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Nov 2022 12:51:44 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10533"; a="590334523" X-IronPort-AV: E=Sophos;i="5.96,169,1665471600"; d="scan'208";a="590334523" Received: from unknown (HELO csl-npg-qt0.la.intel.com) ([10.233.181.103]) by orsmga003.jf.intel.com with ESMTP; 16 Nov 2022 12:51:44 -0800 From: Hernan Vargas To: stable@dpdk.org, ktraynor@redhat.com Cc: nicolas.chautru@intel.com, Hernan Vargas , Maxime Coquelin Subject: [PATCH 21.11 4/7] baseband/acc100: enforce additional check on FCW Date: Wed, 16 Nov 2022 20:46:49 -0800 Message-Id: <20221117044652.163000-5-hernan.vargas@intel.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20221117044652.163000-1-hernan.vargas@intel.com> References: <20221117044652.163000-1-hernan.vargas@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org [ upstream commit 5802f36dd492f4b8c4a270a5d9cc1f11776f1edf ] Enforce additional check on Frame Control Word validity and add stronger alignment for decompression mode. Fixes: 5ad5060f8f7 ("baseband/acc100: add LDPC processing functions") Signed-off-by: Hernan Vargas Reviewed-by: Maxime Coquelin --- drivers/baseband/acc100/rte_acc100_pmd.c | 68 +++++++++++++++++++----- drivers/baseband/acc100/rte_acc100_pmd.h | 2 + 2 files changed, 58 insertions(+), 12 deletions(-) diff --git a/drivers/baseband/acc100/rte_acc100_pmd.c b/drivers/baseband/acc100/rte_acc100_pmd.c index d63d8dd4bc..1fb2d24ded 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.c +++ b/drivers/baseband/acc100/rte_acc100_pmd.c @@ -1294,13 +1294,14 @@ acc100_fcw_td_fill(const struct rte_bbdev_dec_op *op, struct acc100_fcw_td *fcw) /* Fill in a frame control word for LDPC decoding. */ static inline void -acc100_fcw_ld_fill(const struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, +acc100_fcw_ld_fill(struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, union acc100_harq_layout_data *harq_layout) { uint16_t harq_out_length, harq_in_length, ncb_p, k0_p, parity_offset; uint16_t harq_index; uint32_t l; bool harq_prun = false; + uint32_t max_hc_in; fcw->qm = op->ldpc_dec.q_m; fcw->nfiller = op->ldpc_dec.n_filler; @@ -1350,13 +1351,21 @@ acc100_fcw_ld_fill(const struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, harq_in_length = op->ldpc_dec.harq_combined_input.length; if (fcw->hcin_decomp_mode > 0) harq_in_length = harq_in_length * 8 / 6; - harq_in_length = RTE_ALIGN(harq_in_length, 64); - if ((harq_layout[harq_index].offset > 0) & harq_prun) { + harq_in_length = RTE_MIN(harq_in_length, op->ldpc_dec.n_cb + - op->ldpc_dec.n_filler); + + /* Alignment on next 64B - Already enforced from HC output */ + harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, ACC100_HARQ_ALIGN_64B); + + /* Stronger alignment requirement when in decompression mode */ + if (fcw->hcin_decomp_mode > 0) + harq_in_length = RTE_ALIGN_FLOOR(harq_in_length, ACC100_HARQ_ALIGN_COMP); + + if ((harq_layout[harq_index].offset > 0) && harq_prun) { rte_bbdev_log_debug("HARQ IN offset unexpected for now\n"); fcw->hcin_size0 = harq_layout[harq_index].size0; fcw->hcin_offset = harq_layout[harq_index].offset; - fcw->hcin_size1 = harq_in_length - - harq_layout[harq_index].offset; + fcw->hcin_size1 = harq_in_length - harq_layout[harq_index].offset; } else { fcw->hcin_size0 = harq_in_length; fcw->hcin_offset = 0; @@ -1368,6 +1377,21 @@ acc100_fcw_ld_fill(const struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, fcw->hcin_size1 = 0; } + /* Enforce additional check on FCW validity */ + max_hc_in = RTE_ALIGN_CEIL(fcw->ncb - fcw->nfiller, ACC100_HARQ_ALIGN_64B); + if ((fcw->hcin_size0 > max_hc_in) || + (fcw->hcin_size1 + fcw->hcin_offset > max_hc_in) || + ((fcw->hcin_size0 > fcw->hcin_offset) && + (fcw->hcin_size1 != 0))) { + rte_bbdev_log(ERR, " Invalid FCW : HCIn %d %d %d, Ncb %d F %d", + fcw->hcin_size0, fcw->hcin_size1, + fcw->hcin_offset, + fcw->ncb, fcw->nfiller); + /* Disable HARQ input in that case to carry forward */ + op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE; + fcw->hcin_en = 0; + } + fcw->itmax = op->ldpc_dec.iter_max; fcw->itstop = check_bit(op->ldpc_dec.op_flags, RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE); @@ -1392,15 +1416,27 @@ acc100_fcw_ld_fill(const struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, if (fcw->hcout_en > 0) { parity_offset = (op->ldpc_dec.basegraph == 1 ? 20 : 8) * op->ldpc_dec.z_c - op->ldpc_dec.n_filler; - k0_p = (fcw->k0 > parity_offset) ? - fcw->k0 - op->ldpc_dec.n_filler : fcw->k0; + k0_p = (fcw->k0 > parity_offset) ? fcw->k0 - op->ldpc_dec.n_filler : fcw->k0; ncb_p = fcw->ncb - op->ldpc_dec.n_filler; - l = k0_p + fcw->rm_e; + l = RTE_MIN(k0_p + fcw->rm_e, INT16_MAX); harq_out_length = (uint16_t) fcw->hcin_size0; - harq_out_length = RTE_MIN(RTE_MAX(harq_out_length, l), ncb_p); - harq_out_length = (harq_out_length + 0x3F) & 0xFFC0; - if ((k0_p > fcw->hcin_size0 + ACC100_HARQ_OFFSET_THRESHOLD) && - harq_prun) { + harq_out_length = RTE_MAX(harq_out_length, l); + + /* Stronger alignment when in compression mode */ + if (fcw->hcout_comp_mode > 0) + harq_out_length = RTE_ALIGN_CEIL(harq_out_length, ACC100_HARQ_ALIGN_COMP); + + /* Cannot exceed the pruned Ncb circular buffer */ + harq_out_length = RTE_MIN(harq_out_length, ncb_p); + + /* Alignment on next 64B */ + harq_out_length = RTE_ALIGN_CEIL(harq_out_length, ACC100_HARQ_ALIGN_64B); + + /* Stronger alignment when in compression mode enforced again */ + if (fcw->hcout_comp_mode > 0) + harq_out_length = RTE_ALIGN_FLOOR(harq_out_length, ACC100_HARQ_ALIGN_COMP); + + if ((k0_p > fcw->hcin_size0 + ACC100_HARQ_OFFSET_THRESHOLD) && harq_prun) { fcw->hcout_size0 = (uint16_t) fcw->hcin_size0; fcw->hcout_offset = k0_p & 0xFFC0; fcw->hcout_size1 = harq_out_length - fcw->hcout_offset; @@ -1409,6 +1445,14 @@ acc100_fcw_ld_fill(const struct rte_bbdev_dec_op *op, struct acc100_fcw_ld *fcw, fcw->hcout_size1 = 0; fcw->hcout_offset = 0; } + + if (fcw->hcout_size0 == 0) { + rte_bbdev_log(ERR, " Invalid FCW : HCout %d", + fcw->hcout_size0); + op->ldpc_dec.op_flags ^= RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE; + fcw->hcout_en = 0; + } + harq_layout[harq_index].offset = fcw->hcout_offset; harq_layout[harq_index].size0 = fcw->hcout_size0; } else { diff --git a/drivers/baseband/acc100/rte_acc100_pmd.h b/drivers/baseband/acc100/rte_acc100_pmd.h index 071b37cf9d..9dcdf4653b 100644 --- a/drivers/baseband/acc100/rte_acc100_pmd.h +++ b/drivers/baseband/acc100/rte_acc100_pmd.h @@ -170,6 +170,8 @@ #define ACC100_PRQ_DDR_VER 0x10092020 #define ACC100_MS_IN_US (1000) #define ACC100_DDR_TRAINING_MAX (5000) +#define ACC100_HARQ_ALIGN_COMP 256 +#define ACC100_HARQ_ALIGN_64B 64 /* ACC100 DMA Descriptor triplet */ struct acc100_dma_triplet { -- 2.37.1