From: Gregory Etelson <getelson@nvidia.com>
To: <dev@dpdk.org>
Cc: <getelson@nvidia.com>, <matan@nvidia.com>, <rasland@nvidia.com>,
<stable@dpdk.org>, Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Subject: [PATCH 2/2] doc: update MLX5 LRO limitation
Date: Thu, 17 Nov 2022 16:39:01 +0200 [thread overview]
Message-ID: <20221117143901.27957-2-getelson@nvidia.com> (raw)
In-Reply-To: <20221117143901.27957-1-getelson@nvidia.com>
Maximal LRO message size must be multiply of 256.
Otherwise, TCP payload may not fit into a single WQE.
Cc: stable@dpdk.org
Signed-off-by: Gregory Etelson <getelson@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
doc/guides/nics/mlx5.rst | 3 +++
1 file changed, 3 insertions(+)
diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 4f0db21dde..98e0b24be4 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -278,6 +278,9 @@ Limitations
- No Tx metadata go to the E-Switch steering domain for the Flow group 0.
The flows within group 0 and set metadata action are rejected by hardware.
+- The driver rounds down the ``max_lro_pkt_size`` value in the port
+ configuration to a multiple of 256 due to HW limitation.
+
.. note::
MAC addresses not already present in the bridge table of the associated
--
2.34.1
next parent reply other threads:[~2022-11-17 14:39 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20221117143901.27957-1-getelson@nvidia.com>
2022-11-17 14:39 ` Gregory Etelson [this message]
2022-11-21 15:23 ` Thomas Monjalon
2022-11-22 5:17 ` Gregory Etelson
2022-11-22 8:25 ` Thomas Monjalon
[not found] ` <20221122051308.194-1-getelson@nvidia.com>
2022-11-22 5:13 ` [PATCH v2 " Gregory Etelson
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