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From: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
To: <dev@dpdk.org>
Cc: <matan@nvidia.com>, <rasland@nvidia.com>, <orika@nvidia.com>,
	<stable@dpdk.org>
Subject: [PATCH] net/mlx5: fix wait descriptor opcode for ConnectX-7
Date: Tue, 3 Jan 2023 13:10:41 +0200	[thread overview]
Message-ID: <20230103111041.28802-1-viacheslavo@nvidia.com> (raw)

Since ConnectX-7 the special hardware capability to schedule
packet sending on specified time is provided. It uses special
WAIT WQE (hardware descriptor) with wait condition defined
by opcode. The CYCLIC_BIGGER was wrongly used instead of
CYCLIC_SMALLER. This caused arbitrary and stale time shift
in traffic scheduling.

Fixes: 49e8797619e40 ("net/mlx5: support wait on time in Tx")
Cc: stable@dpdk.org

Signed-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
---
 drivers/net/mlx5/mlx5_tx.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/mlx5/mlx5_tx.h b/drivers/net/mlx5/mlx5_tx.h
index a44050a1ce..a056be7ca8 100644
--- a/drivers/net/mlx5/mlx5_tx.h
+++ b/drivers/net/mlx5/mlx5_tx.h
@@ -817,7 +817,7 @@ mlx5_tx_wseg_init(struct mlx5_txq_data *restrict txq,
 	struct mlx5_wqe_wseg *ws;
 
 	ws = RTE_PTR_ADD(wqe, MLX5_WSEG_SIZE);
-	ws->operation = rte_cpu_to_be_32(MLX5_WAIT_COND_CYCLIC_BIGGER);
+	ws->operation = rte_cpu_to_be_32(MLX5_WAIT_COND_CYCLIC_SMALLER);
 	ws->lkey = RTE_BE32(0);
 	ws->va_high = RTE_BE32(0);
 	ws->va_low = RTE_BE32(0);
-- 
2.18.1


             reply	other threads:[~2023-01-03 11:11 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-01-03 11:10 Viacheslav Ovsiienko [this message]
2023-01-08 12:58 ` Raslan Darawsheh

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