From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id ECF04423F2 for ; Mon, 16 Jan 2023 16:37:41 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DC76D42D18; Mon, 16 Jan 2023 16:37:41 +0100 (CET) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mails.dpdk.org (Postfix) with ESMTP id A9D1C40F18; Mon, 16 Jan 2023 16:37:40 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1673883461; x=1705419461; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mbIx9zd3vsxExwZmUhZ4YT8HslOf+mQIXJW29tDJsFs=; b=CfRq06VXHwN2NibAPU4j2n+jgJLdUXWROc5a4WFyayHNrGThpMuXneVA bA/I1bfZRdW7iUEMEkg5Ou3xEJJ4kD00SfQjVmzgqZnzG17jTsEIn3dj5 1sW6JoqkwOP0iH6gK7vKmVH/cjShRDul/JX5LXH025+Nb7rELopRUWCFF lPnOQx9K5bxndTjaSrm5YdUkfhhB1+oCsW2shw9w7qx7ctt5pM8DYpfsu YMLbVskX5YpiKVYJKnFsCEgzAlXHJCi0iEzK7nAbtpDFFLU7nUkaOO5jQ 9kDAJ/t4x/IaW8VoAiuJcSsJGxb/yqvXKB/5ZzzDWV2ApdaJYxti3te5b Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10592"; a="351735360" X-IronPort-AV: E=Sophos;i="5.97,221,1669104000"; d="scan'208";a="351735360" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jan 2023 07:37:40 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10592"; a="727505469" X-IronPort-AV: E=Sophos;i="5.97,221,1669104000"; d="scan'208";a="727505469" Received: from silpixa00401385.ir.intel.com ([10.237.214.55]) by fmsmga004.fm.intel.com with ESMTP; 16 Jan 2023 07:37:39 -0800 From: Bruce Richardson To: dev@dpdk.org Cc: Bruce Richardson , conor.walsh@intel.com, stable@dpdk.org, Kevin Laatz Subject: [PATCH 2/5] dma/ioat: fix incorrectly set indexes after restart Date: Mon, 16 Jan 2023 15:37:11 +0000 Message-Id: <20230116153714.554470-3-bruce.richardson@intel.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230116153714.554470-1-bruce.richardson@intel.com> References: <20230116153714.554470-1-bruce.richardson@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org As part of the process of restarting a dma instance, the IOAT driver will reset the HW addresses and state values. The read and write indexes for SW use need to be similarly reset to keep HW and SW in sync. Fixes: 583f046dd404 ("dma/ioat: add start and stop") Cc: conor.walsh@intel.com Cc: stable@dpdk.org Signed-off-by: Bruce Richardson --- drivers/dma/ioat/ioat_dmadev.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/dma/ioat/ioat_dmadev.c b/drivers/dma/ioat/ioat_dmadev.c index aff7bbbfde..072eb17cd9 100644 --- a/drivers/dma/ioat/ioat_dmadev.c +++ b/drivers/dma/ioat/ioat_dmadev.c @@ -146,6 +146,13 @@ ioat_dev_start(struct rte_dma_dev *dev) /* Prime the status register to be set to the last element. */ ioat->status = ioat->ring_addr + ((ioat->qcfg.nb_desc - 1) * DESC_SZ); + /* reset all counters */ + ioat->next_read = 0; + ioat->next_write = 0; + ioat->last_write = 0; + ioat->offset = 0; + ioat->failure = 0; + printf("IOAT.status: %s [0x%"PRIx64"]\n", chansts_readable[ioat->status & IOAT_CHANSTS_STATUS], ioat->status); -- 2.37.2