From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0C33F41C56 for ; Thu, 9 Feb 2023 23:23:14 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 3179C42D0C; Thu, 9 Feb 2023 23:23:13 +0100 (CET) Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mails.dpdk.org (Postfix) with ESMTP id BE27E40E50; Thu, 9 Feb 2023 23:23:07 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1675981388; x=1707517388; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=b7bPRW3CJRVx4M5VHU/rFWfIcqtpIC93vn6D7qN4+CU=; b=PHFIhTVZ1gqP/NVO0zALUGrxQr6Xdkk3lgKBK7AVY/We+oqQHAorvjWR sOMfCsi7H2Gy0ztqCVJAaHdTMHW6V2DJvFyHQ7MMHO0t0SFcqIPrD8jUO hHTi4owSoHaGN9/lsXdy+zPvQ8RxsJ6yQgZcWdSrYuxCKsqlsHC/oBu0O NIuNr+jEgG28JIM4Es57s562/4bunV44V9TYCvXSwXJNmDpNd6eBp/yEl WyrZcyxAJRa20ycVL6z51TD+se44GDPh1yD19QZcLBiSlJMvVvgWlptEN 3EbSqB6ey2wpW8a4oTYfeSryy/VrV8lSySJJjGEsmyonsiEGZqDqSVUS9 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10616"; a="331563032" X-IronPort-AV: E=Sophos;i="5.97,285,1669104000"; d="scan'208";a="331563032" Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2023 14:23:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10616"; a="736513264" X-IronPort-AV: E=Sophos;i="5.97,285,1669104000"; d="scan'208";a="736513264" Received: from spr-npg-bds1-eec2.sn.intel.com (HELO spr-npg-bds1-eec2..) ([10.233.181.123]) by fmsmga004.fm.intel.com with ESMTP; 09 Feb 2023 14:23:05 -0800 From: Nicolas Chautru To: dev@dpdk.org, maxime.coquelin@redhat.com Cc: hernan.vargas@intel.com, stable@dpdk.or, Nicolas Chautru , stable@dpdk.org Subject: [PATCH v1 2/9] baseband/acc: add support for 4GUL with SO and TB Date: Thu, 9 Feb 2023 22:19:22 +0000 Message-Id: <20230209221929.265059-3-nicolas.chautru@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230209221929.265059-1-nicolas.chautru@intel.com> References: <20230209221929.265059-1-nicolas.chautru@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Implementation to support the case when using LTE decoder with soft output and transport block mode. Fixes: bec597b78a0 ("baseband/acc200: add LTE processing") Cc: stable@dpdk.org Signed-off-by: Nicolas Chautru --- drivers/baseband/acc/rte_vrb_pmd.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/baseband/acc/rte_vrb_pmd.c b/drivers/baseband/acc/rte_vrb_pmd.c index 797330a5dd..c43c08afe8 100644 --- a/drivers/baseband/acc/rte_vrb_pmd.c +++ b/drivers/baseband/acc/rte_vrb_pmd.c @@ -1190,15 +1190,12 @@ vrb_fcw_td_fill(const struct rte_bbdev_dec_op *op, struct acc_fcw_td *fcw) fcw->bypass_sb_deint = !check_bit(op->turbo_dec.op_flags, RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE); if (op->turbo_dec.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) { - /* FIXME for TB block */ + fcw->c = op->turbo_dec.tb_params.c; fcw->k_pos = op->turbo_dec.tb_params.k_pos; - fcw->k_neg = op->turbo_dec.tb_params.k_neg; } else { + fcw->c = 1; fcw->k_pos = op->turbo_dec.cb_params.k; - fcw->k_neg = op->turbo_dec.cb_params.k; } - fcw->c = 1; - fcw->c_neg = 1; if (check_bit(op->turbo_dec.op_flags, RTE_BBDEV_TURBO_SOFT_OUTPUT)) { fcw->soft_output_en = 1; fcw->sw_soft_out_dis = 0; @@ -1209,8 +1206,14 @@ vrb_fcw_td_fill(const struct rte_bbdev_dec_op *op, struct acc_fcw_td *fcw) if (check_bit(op->turbo_dec.op_flags, RTE_BBDEV_TURBO_EQUALIZER)) { fcw->bypass_teq = 0; - fcw->ea = op->turbo_dec.cb_params.e; - fcw->eb = op->turbo_dec.cb_params.e; + if (op->turbo_dec.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) { + fcw->cab = op->turbo_dec.tb_params.cab; + fcw->ea = op->turbo_dec.tb_params.ea; + fcw->eb = op->turbo_dec.tb_params.eb; + } else { + fcw->ea = op->turbo_dec.cb_params.e; + fcw->eb = op->turbo_dec.cb_params.e; + } if (op->turbo_dec.rv_index == 0) fcw->k0_start_col = ACC_FCW_TD_RVIDX_0; else if (op->turbo_dec.rv_index == 1) @@ -1387,9 +1390,7 @@ vrb_dma_desc_td_fill(struct rte_bbdev_dec_op *op, desc->numCBs = 1; if (op->turbo_dec.code_block_mode == RTE_BBDEV_TRANSPORT_BLOCK) { - k = (r < op->turbo_dec.tb_params.c_neg) - ? op->turbo_dec.tb_params.k_neg - : op->turbo_dec.tb_params.k_pos; + k = op->turbo_dec.tb_params.k_pos; e = (r < op->turbo_dec.tb_params.cab) ? op->turbo_dec.tb_params.ea : op->turbo_dec.tb_params.eb; -- 2.34.1