From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9A93542CBC for ; Thu, 15 Jun 2023 03:34:27 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 9475942D44; Thu, 15 Jun 2023 03:34:27 +0200 (CEST) Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) by mails.dpdk.org (Postfix) with ESMTP id C2A5D40E0F for ; Thu, 15 Jun 2023 03:34:25 +0200 (CEST) Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-3f8c65020dfso14557395e9.2 for ; Wed, 14 Jun 2023 18:34:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1686792865; x=1689384865; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JbIIGSq80Tidkm36/9TceMFLbSIbWZd/nbnrmjd4S+U=; b=jRrWxOrkrtubqKrE44Wd4TuTHK/iFVFszxzd39nHf5wD6ygVfTcIu5GCgAsqJZTESK kUWG5sna4O6jIBNtraEvrBCYR21qWF1rXgeIM7/f2sb7YGMFcNyVTsCQWmfkw+Dvq/Tj cuENynvgWyLuEm9sbj1owzvEgknDPj931OxJCwf9DY3bJTL0hX8G4JwxcOmR8vKkLNVf 0/o/5yuXT29/llbSKkNoZu6xvaz8QE2TqMzYYSg0h0Hgd2SOf5w9KSUQugm0dqOPT35b PQL1e6l9/+GRqsTyQmrJQspPgHB+wnt3zrd4LcKd/8qRCGWNjBmdPTCSVcIvcpUAlneE NGfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686792865; x=1689384865; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JbIIGSq80Tidkm36/9TceMFLbSIbWZd/nbnrmjd4S+U=; b=J2H1tzyYmsa3zE1TQyDHzV5BD/9kPnVB5mKCZKcoWvWIX00AwbTKmMLhWLNCsExY5H Z2Kvfyn1QopSuvX5bBHemqQxsfmj8Eb4D9fL36Ze6mf6+wivuFY2LHxIWFXjGwmEUhJh J0t7rYwqW0H/mv4mhCV4hSMZT77VCBpMnmUO0ym6hzdTyuOnkNYi0Je9gOTR77fW0B3l C32F5/hwDHbSf3TIwcZQxwQ2xXLG3TthA1q1ZQy7q6Pzus/cW8c2qKJpTmmz8RK7DOLZ nko/JNdwMnZRQcw5NBjGozegGab3tSzCrVsUCQnbvuq2EbFO/3y1EJJdYEDgnMTGbNFU DbCg== X-Gm-Message-State: AC+VfDwVExfdSULKuDpqVXOBfi7G/VOjJvmSY6o0fRPd4HpHHoQ/zYMV v05qc1/1i4k57IDMH65eZIpDMHrZyt0YnuqX X-Google-Smtp-Source: ACHHUZ7KRMS3y3WSPiZJj7hZpVDChtkvWSkIOI1W5iih1HikEzSmPnHnGVeW+jE+OEbWhp7Gh0srdA== X-Received: by 2002:adf:f642:0:b0:30d:5f9e:c29f with SMTP id x2-20020adff642000000b0030d5f9ec29fmr10526662wrp.37.1686792865382; Wed, 14 Jun 2023 18:34:25 -0700 (PDT) Received: from localhost ([2a01:4b00:d307:1000:f1d3:eb5e:11f4:a7d9]) by smtp.gmail.com with ESMTPSA id e4-20020adfdbc4000000b0030ada01ca78sm19499533wrj.10.2023.06.14.18.34.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jun 2023 18:34:24 -0700 (PDT) From: luca.boccassi@gmail.com To: Chengwen Feng Cc: Dongdong Liu , dpdk stable Subject: patch 'net/hns3: fix Rx multiple firmware reset interrupts' has been queued to stable release 20.11.9 Date: Thu, 15 Jun 2023 02:32:23 +0100 Message-Id: <20230615013258.1439718-28-luca.boccassi@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230615013258.1439718-1-luca.boccassi@gmail.com> References: <20230615013258.1439718-1-luca.boccassi@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 20.11.9 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 06/17/23. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://github.com/bluca/dpdk-stable This queued commit can be viewed at: https://github.com/bluca/dpdk-stable/commit/cce2668a9359a171d9742886b0db905aeb094586 Thanks. Luca Boccassi --- >From cce2668a9359a171d9742886b0db905aeb094586 Mon Sep 17 00:00:00 2001 From: Chengwen Feng Date: Mon, 22 May 2023 21:17:39 +0800 Subject: [PATCH] net/hns3: fix Rx multiple firmware reset interrupts [ upstream commit e3c71325cec3353c4b9623310ece363a7c79604f ] In the firmware (also known as IMP) reset scenario, driver interrupt processing and firmware watchdog initialization are asynchronous. If the driver interrupt processing is faster than firmware watchdog initialization (that is, the driver clears the firmware reset interrupt source before the firmware watchdog is initialized), the driver will receive multiple firmware reset interrupts. In the Kunpeng 920 platform, the above situation does not exist. But it does on the newer platforms. So we add 5ms delay before drivers clears the IMP reset interrupt source. As for the impact of 5ms, the number of PFs managed by a firmware is limited. Therefore, even if a DPDK process takes over all the PFs which managed by the firmware, the delay is controllable. Fixes: ee930d38ffca ("net/hns3: fix timing of clearing interrupt source") Signed-off-by: Chengwen Feng Signed-off-by: Dongdong Liu --- drivers/net/hns3/hns3_ethdev.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 1ffa67f9e7..5561e80045 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -226,6 +226,19 @@ hns3_clear_all_event_cause(struct hns3_hw *hw) hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0); } +static void +hns3_delay_before_clear_event_cause(struct hns3_hw *hw, uint32_t event_type, uint32_t regclr) +{ +#define IMPRESET_WAIT_MS_TIME 5 + + if (event_type == HNS3_VECTOR0_EVENT_RST && + regclr & BIT(HNS3_VECTOR0_IMPRESET_INT_B) && + hw->revision >= PCI_REVISION_ID_HIP09_A) { + rte_delay_ms(IMPRESET_WAIT_MS_TIME); + hns3_dbg(hw, "wait firmware watchdog initialization completed."); + } +} + static void hns3_interrupt_handler(void *param) { @@ -239,6 +252,7 @@ hns3_interrupt_handler(void *param) hns3_pf_disable_irq0(hw); event_cause = hns3_check_event_cause(hns, &clearval); + hns3_delay_before_clear_event_cause(hw, event_cause, clearval); hns3_clear_event_cause(hw, event_cause, clearval); /* vector 0 interrupt is shared with reset and mailbox source events. */ if (event_cause == HNS3_VECTOR0_EVENT_ERR) { -- 2.39.2 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2023-06-15 01:56:36.220911976 +0100 +++ 0028-net-hns3-fix-Rx-multiple-firmware-reset-interrupts.patch 2023-06-15 01:56:34.583541653 +0100 @@ -1 +1 @@ -From e3c71325cec3353c4b9623310ece363a7c79604f Mon Sep 17 00:00:00 2001 +From cce2668a9359a171d9742886b0db905aeb094586 Mon Sep 17 00:00:00 2001 @@ -5,0 +6,2 @@ +[ upstream commit e3c71325cec3353c4b9623310ece363a7c79604f ] + @@ -23 +24,0 @@ -Cc: stable@dpdk.org @@ -32 +33 @@ -index 5ef66f96c6..664226a6ef 100644 +index 1ffa67f9e7..5561e80045 100644 @@ -35,2 +36,2 @@ -@@ -286,6 +286,19 @@ hns3_handle_mac_tnl(struct hns3_hw *hw) - } +@@ -226,6 +226,19 @@ hns3_clear_all_event_cause(struct hns3_hw *hw) + hns3_clear_event_cause(hw, HNS3_VECTOR0_EVENT_MBX, 0); @@ -55,4 +56,4 @@ -@@ -305,6 +318,7 @@ hns3_interrupt_handler(void *param) - vector0_int = hns3_read_dev(hw, HNS3_VECTOR0_OTHER_INT_STS_REG); - ras_int = hns3_read_dev(hw, HNS3_RAS_PF_OTHER_INT_STS_REG); - cmdq_int = hns3_read_dev(hw, HNS3_VECTOR0_CMDQ_SRC_REG); +@@ -239,6 +252,7 @@ hns3_interrupt_handler(void *param) + hns3_pf_disable_irq0(hw); + + event_cause = hns3_check_event_cause(hns, &clearval);