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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by DS1PEPF00017093.mail.protection.outlook.com (10.167.17.136) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6933.15 via Frontend Transport; Sun, 22 Oct 2023 14:27:18 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Sun, 22 Oct 2023 07:27:11 -0700 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Sun, 22 Oct 2023 07:27:10 -0700 From: Xueming Li To: Ciara Power CC: dpdk stable Subject: patch 'crypto/qat: fix raw API null algorithm digest' has been queued to stable release 22.11.4 Date: Sun, 22 Oct 2023 22:21:17 +0800 Message-ID: <20231022142250.10324-49-xuemingl@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231022142250.10324-1-xuemingl@nvidia.com> References: <20231022142250.10324-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017093:EE_|IA1PR12MB6065:EE_ X-MS-Office365-Filtering-Correlation-Id: f8c11edf-fffe-4767-0340-08dbd30afee7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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SFS:(13230031)(4636009)(396003)(346002)(39860400002)(136003)(376002)(230922051799003)(186009)(64100799003)(82310400011)(1800799009)(451199024)(40470700004)(46966006)(36840700001)(36860700001)(7636003)(356005)(336012)(426003)(26005)(82740400003)(16526019)(6286002)(47076005)(40460700003)(5660300002)(55016003)(83380400001)(4326008)(316002)(30864003)(86362001)(8676002)(70206006)(8936002)(1076003)(6916009)(41300700001)(4001150100001)(70586007)(7696005)(966005)(53546011)(478600001)(2906002)(40480700001)(2616005)(36756003); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Oct 2023 14:27:18.1337 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f8c11edf-fffe-4767-0340-08dbd30afee7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017093.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6065 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 22.11.4 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 11/15/23. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://git.dpdk.org/dpdk-stable/log/?h=22.11-staging This queued commit can be viewed at: https://git.dpdk.org/dpdk-stable/commit/?h=22.11-staging&id=40ea03b5eaf1339200b0722a349b0896929aa25b Thanks. Xueming Li --- >From 40ea03b5eaf1339200b0722a349b0896929aa25b Mon Sep 17 00:00:00 2001 From: Ciara Power Date: Thu, 7 Sep 2023 15:35:53 +0000 Subject: [PATCH] crypto/qat: fix raw API null algorithm digest Cc: Xueming Li [ upstream commit d7d52b37e89132f07121323c449ac838e6448ae0 ] QAT HW generates bytes of 0x00 digest, even when a digest of len 0 is requested for NULL. This caused test failures when the test vector had digest len 0, as the buffer has unexpected changed bytes. By placing the digest into the cookie for NULL authentication, the buffer remains unchanged as expected, and the digest is placed to the side, as it won't be used anyway. This fix was previously added for the main QAT code path, but it also needs to be included for the raw API code path. Fixes: db0e952a5c01 ("crypto/qat: add NULL capability") Signed-off-by: Ciara Power --- drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 19 ++++++++- drivers/crypto/qat/dev/qat_sym_pmd_gen1.c | 41 +++++++++++++++++--- 2 files changed, 53 insertions(+), 7 deletions(-) diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c index 1f6f63c831..84d58accc7 100644 --- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c +++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c @@ -605,6 +605,8 @@ qat_sym_dp_enqueue_single_auth_gen3(void *qp_data, uint8_t *drv_ctx, struct icp_qat_fw_la_bulk_req *req; int32_t data_len; uint32_t tail = dp_ctx->tail; + struct rte_crypto_va_iova_ptr null_digest; + struct rte_crypto_va_iova_ptr *job_digest = digest; req = (struct icp_qat_fw_la_bulk_req *)( (uint8_t *)tx_queue->base_addr + tail); @@ -618,7 +620,12 @@ qat_sym_dp_enqueue_single_auth_gen3(void *qp_data, uint8_t *drv_ctx, if (unlikely(data_len < 0)) return -1; - enqueue_one_auth_job_gen3(ctx, cookie, req, digest, auth_iv, ofs, + if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) { + null_digest.iova = cookie->digest_null_phys_addr; + job_digest = &null_digest; + } + + enqueue_one_auth_job_gen3(ctx, cookie, req, job_digest, auth_iv, ofs, (uint32_t)data_len); dp_ctx->tail = tail; @@ -640,6 +647,8 @@ qat_sym_dp_enqueue_auth_jobs_gen3(void *qp_data, uint8_t *drv_ctx, uint32_t tail; struct icp_qat_fw_la_bulk_req *req; int32_t data_len; + struct rte_crypto_va_iova_ptr null_digest; + struct rte_crypto_va_iova_ptr *job_digest = NULL; n = QAT_SYM_DP_GET_MAX_ENQ(qp, dp_ctx->cached_enqueue, vec->num); if (unlikely(n == 0)) { @@ -672,7 +681,13 @@ qat_sym_dp_enqueue_auth_jobs_gen3(void *qp_data, uint8_t *drv_ctx, if (unlikely(data_len < 0)) break; - enqueue_one_auth_job_gen3(ctx, cookie, req, &vec->digest[i], + if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) { + null_digest.iova = cookie->digest_null_phys_addr; + job_digest = &null_digest; + } else + job_digest = &vec->digest[i]; + + enqueue_one_auth_job_gen3(ctx, cookie, req, job_digest, &vec->auth_iv[i], ofs, (uint32_t)data_len); tail = (tail + tx_queue->msg_size) & tx_queue->modulo_mask; } diff --git a/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c b/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c index 2709b0ab04..888dea4ad9 100644 --- a/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c +++ b/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c @@ -607,6 +607,8 @@ qat_sym_dp_enqueue_single_auth_gen1(void *qp_data, uint8_t *drv_ctx, struct icp_qat_fw_la_bulk_req *req; int32_t data_len; uint32_t tail = dp_ctx->tail; + struct rte_crypto_va_iova_ptr null_digest; + struct rte_crypto_va_iova_ptr *job_digest = digest; req = (struct icp_qat_fw_la_bulk_req *)( (uint8_t *)tx_queue->base_addr + tail); @@ -620,8 +622,13 @@ qat_sym_dp_enqueue_single_auth_gen1(void *qp_data, uint8_t *drv_ctx, if (unlikely(data_len < 0)) return -1; - enqueue_one_auth_job_gen1(ctx, req, digest, auth_iv, ofs, - (uint32_t)data_len); + if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) { + null_digest.iova = cookie->digest_null_phys_addr; + job_digest = &null_digest; + } + + enqueue_one_auth_job_gen1(ctx, req, job_digest, auth_iv, ofs, + (uint32_t)data_len); dp_ctx->tail = tail; dp_ctx->cached_enqueue++; @@ -646,6 +653,8 @@ qat_sym_dp_enqueue_auth_jobs_gen1(void *qp_data, uint8_t *drv_ctx, uint32_t tail; struct icp_qat_fw_la_bulk_req *req; int32_t data_len; + struct rte_crypto_va_iova_ptr null_digest; + struct rte_crypto_va_iova_ptr *job_digest = NULL; n = QAT_SYM_DP_GET_MAX_ENQ(qp, dp_ctx->cached_enqueue, vec->num); if (unlikely(n == 0)) { @@ -678,7 +687,14 @@ qat_sym_dp_enqueue_auth_jobs_gen1(void *qp_data, uint8_t *drv_ctx, if (unlikely(data_len < 0)) break; - enqueue_one_auth_job_gen1(ctx, req, &vec->digest[i], + + if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) { + null_digest.iova = cookie->digest_null_phys_addr; + job_digest = &null_digest; + } else + job_digest = &vec->digest[i]; + + enqueue_one_auth_job_gen1(ctx, req, job_digest, &vec->auth_iv[i], ofs, (uint32_t)data_len); tail = (tail + tx_queue->msg_size) & tx_queue->modulo_mask; @@ -715,6 +731,8 @@ qat_sym_dp_enqueue_single_chain_gen1(void *qp_data, uint8_t *drv_ctx, struct icp_qat_fw_la_bulk_req *req; int32_t data_len; uint32_t tail = dp_ctx->tail; + struct rte_crypto_va_iova_ptr null_digest; + struct rte_crypto_va_iova_ptr *job_digest = digest; req = (struct icp_qat_fw_la_bulk_req *)( (uint8_t *)tx_queue->base_addr + tail); @@ -727,8 +745,13 @@ qat_sym_dp_enqueue_single_chain_gen1(void *qp_data, uint8_t *drv_ctx, if (unlikely(data_len < 0)) return -1; + if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) { + null_digest.iova = cookie->digest_null_phys_addr; + job_digest = &null_digest; + } + if (unlikely(enqueue_one_chain_job_gen1(ctx, req, data, n_data_vecs, - NULL, 0, cipher_iv, digest, auth_iv, ofs, + NULL, 0, cipher_iv, job_digest, auth_iv, ofs, (uint32_t)data_len))) return -1; @@ -756,6 +779,8 @@ qat_sym_dp_enqueue_chain_jobs_gen1(void *qp_data, uint8_t *drv_ctx, uint32_t tail; struct icp_qat_fw_la_bulk_req *req; int32_t data_len; + struct rte_crypto_va_iova_ptr null_digest; + struct rte_crypto_va_iova_ptr *job_digest; n = QAT_SYM_DP_GET_MAX_ENQ(qp, dp_ctx->cached_enqueue, vec->num); if (unlikely(n == 0)) { @@ -789,10 +814,16 @@ qat_sym_dp_enqueue_chain_jobs_gen1(void *qp_data, uint8_t *drv_ctx, if (unlikely(data_len < 0)) break; + if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) { + null_digest.iova = cookie->digest_null_phys_addr; + job_digest = &null_digest; + } else + job_digest = &vec->digest[i]; + if (unlikely(enqueue_one_chain_job_gen1(ctx, req, vec->src_sgl[i].vec, vec->src_sgl[i].num, NULL, 0, - &vec->iv[i], &vec->digest[i], + &vec->iv[i], job_digest, &vec->auth_iv[i], ofs, (uint32_t)data_len))) break; -- 2.25.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2023-10-22 22:17:36.206129300 +0800 +++ 0048-crypto-qat-fix-raw-API-null-algorithm-digest.patch 2023-10-22 22:17:34.266723700 +0800 @@ -1 +1 @@ -From d7d52b37e89132f07121323c449ac838e6448ae0 Mon Sep 17 00:00:00 2001 +From 40ea03b5eaf1339200b0722a349b0896929aa25b Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Xueming Li + +[ upstream commit d7d52b37e89132f07121323c449ac838e6448ae0 ] @@ -18 +20,0 @@ -Cc: stable@dpdk.org @@ -27 +29 @@ -index d25e1b2f3a..0a939161f9 100644 +index 1f6f63c831..84d58accc7 100644 @@ -30 +32 @@ -@@ -637,6 +637,8 @@ qat_sym_dp_enqueue_single_auth_gen3(void *qp_data, uint8_t *drv_ctx, +@@ -605,6 +605,8 @@ qat_sym_dp_enqueue_single_auth_gen3(void *qp_data, uint8_t *drv_ctx, @@ -39 +41 @@ -@@ -650,7 +652,12 @@ qat_sym_dp_enqueue_single_auth_gen3(void *qp_data, uint8_t *drv_ctx, +@@ -618,7 +620,12 @@ qat_sym_dp_enqueue_single_auth_gen3(void *qp_data, uint8_t *drv_ctx, @@ -53 +55 @@ -@@ -672,6 +679,8 @@ qat_sym_dp_enqueue_auth_jobs_gen3(void *qp_data, uint8_t *drv_ctx, +@@ -640,6 +647,8 @@ qat_sym_dp_enqueue_auth_jobs_gen3(void *qp_data, uint8_t *drv_ctx, @@ -62 +64 @@ -@@ -704,7 +713,13 @@ qat_sym_dp_enqueue_auth_jobs_gen3(void *qp_data, uint8_t *drv_ctx, +@@ -672,7 +681,13 @@ qat_sym_dp_enqueue_auth_jobs_gen3(void *qp_data, uint8_t *drv_ctx, @@ -78 +80 @@ -index 70938ba508..e4bcfa59e7 100644 +index 2709b0ab04..888dea4ad9 100644 @@ -81 +83 @@ -@@ -598,6 +598,8 @@ qat_sym_dp_enqueue_single_auth_gen1(void *qp_data, uint8_t *drv_ctx, +@@ -607,6 +607,8 @@ qat_sym_dp_enqueue_single_auth_gen1(void *qp_data, uint8_t *drv_ctx, @@ -90 +92 @@ -@@ -611,8 +613,13 @@ qat_sym_dp_enqueue_single_auth_gen1(void *qp_data, uint8_t *drv_ctx, +@@ -620,8 +622,13 @@ qat_sym_dp_enqueue_single_auth_gen1(void *qp_data, uint8_t *drv_ctx, @@ -106 +108 @@ -@@ -636,6 +643,8 @@ qat_sym_dp_enqueue_auth_jobs_gen1(void *qp_data, uint8_t *drv_ctx, +@@ -646,6 +653,8 @@ qat_sym_dp_enqueue_auth_jobs_gen1(void *qp_data, uint8_t *drv_ctx, @@ -115 +117 @@ -@@ -668,7 +677,14 @@ qat_sym_dp_enqueue_auth_jobs_gen1(void *qp_data, uint8_t *drv_ctx, +@@ -678,7 +687,14 @@ qat_sym_dp_enqueue_auth_jobs_gen1(void *qp_data, uint8_t *drv_ctx, @@ -131 +133 @@ -@@ -703,6 +719,8 @@ qat_sym_dp_enqueue_single_chain_gen1(void *qp_data, uint8_t *drv_ctx, +@@ -715,6 +731,8 @@ qat_sym_dp_enqueue_single_chain_gen1(void *qp_data, uint8_t *drv_ctx, @@ -140 +142 @@ -@@ -715,8 +733,13 @@ qat_sym_dp_enqueue_single_chain_gen1(void *qp_data, uint8_t *drv_ctx, +@@ -727,8 +745,13 @@ qat_sym_dp_enqueue_single_chain_gen1(void *qp_data, uint8_t *drv_ctx, @@ -155 +157 @@ -@@ -743,6 +766,8 @@ qat_sym_dp_enqueue_chain_jobs_gen1(void *qp_data, uint8_t *drv_ctx, +@@ -756,6 +779,8 @@ qat_sym_dp_enqueue_chain_jobs_gen1(void *qp_data, uint8_t *drv_ctx, @@ -164 +166 @@ -@@ -776,10 +801,16 @@ qat_sym_dp_enqueue_chain_jobs_gen1(void *qp_data, uint8_t *drv_ctx, +@@ -789,10 +814,16 @@ qat_sym_dp_enqueue_chain_jobs_gen1(void *qp_data, uint8_t *drv_ctx,