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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000EE3E.mail.protection.outlook.com (10.167.242.18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7091.18 via Frontend Transport; Mon, 11 Dec 2023 10:18:45 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 11 Dec 2023 02:18:33 -0800 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Mon, 11 Dec 2023 02:18:31 -0800 From: Xueming Li To: Abdullah Sevincer CC: dpdk stable Subject: patch 'bus/pci: add PASID control' has been queued to stable release 22.11.4 Date: Mon, 11 Dec 2023 18:11:30 +0800 Message-ID: <20231211101226.2122-66-xuemingl@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231211101226.2122-1-xuemingl@nvidia.com> References: <20231022142250.10324-1-xuemingl@nvidia.com> <20231211101226.2122-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3E:EE_|SA0PR12MB4573:EE_ X-MS-Office365-Filtering-Correlation-Id: 3a8b6b37-80de-49b3-c518-08dbfa328eb4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230031)(4636009)(39860400002)(396003)(136003)(376002)(346002)(230273577357003)(230173577357003)(230922051799003)(64100799003)(82310400011)(1800799012)(451199024)(186009)(40470700004)(36840700001)(46966006)(4001150100001)(7696005)(2906002)(70206006)(6916009)(53546011)(7636003)(356005)(36756003)(86362001)(316002)(8936002)(4326008)(8676002)(5660300002)(55016003)(40480700001)(70586007)(966005)(478600001)(40460700003)(41300700001)(36860700001)(82740400003)(47076005)(6286002)(26005)(336012)(426003)(1076003)(2616005)(83380400001)(16526019); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Dec 2023 10:18:45.1171 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3a8b6b37-80de-49b3-c518-08dbfa328eb4 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3E.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB4573 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 22.11.4 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 12/13/23. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://git.dpdk.org/dpdk-stable/log/?h=22.11-staging This queued commit can be viewed at: https://git.dpdk.org/dpdk-stable/commit/?h=22.11-staging&id=5586a7be436c18b55d006ad4c21cca5ef403eb91 Thanks. Xueming Li --- >From 5586a7be436c18b55d006ad4c21cca5ef403eb91 Mon Sep 17 00:00:00 2001 From: Abdullah Sevincer Date: Mon, 6 Nov 2023 11:05:20 -0600 Subject: [PATCH] bus/pci: add PASID control Cc: Xueming Li [ upstream commit 60ea19609aecbd644d7ad7cb86ae06dd76291cf9 ] Add an internal API to control PASID for a given PCIe device. For kernels when PASID enabled by default it breaks DLB functionality, hence disabling PASID is required for DLB to function properly. PASID capability is not exposed to users hence offset can not be retrieved by rte_pci_find_ext_capability() API. Therefore, API implemented in this commit accepts an offset for PASID with an enable flag which is used to enable/disable PASID. Signed-off-by: Abdullah Sevincer --- drivers/bus/pci/pci_common.c | 10 ++++++++++ drivers/bus/pci/rte_bus_pci.h | 14 ++++++++++++++ drivers/bus/pci/version.map | 1 + lib/pci/rte_pci.h | 4 ++++ 4 files changed, 29 insertions(+) diff --git a/drivers/bus/pci/pci_common.c b/drivers/bus/pci/pci_common.c index e83d77090b..756e308fdf 100644 --- a/drivers/bus/pci/pci_common.c +++ b/drivers/bus/pci/pci_common.c @@ -884,6 +884,16 @@ rte_pci_set_bus_master(struct rte_pci_device *dev, bool enable) return 0; } +int +rte_pci_pasid_set_state(const struct rte_pci_device *dev, + off_t offset, bool enable) +{ + uint16_t pasid = enable; + return rte_pci_write_config(dev, &pasid, sizeof(pasid), offset) < 0 + ? -1 + : 0; +} + struct rte_pci_bus rte_pci_bus = { .bus = { .scan = rte_pci_scan, diff --git a/drivers/bus/pci/rte_bus_pci.h b/drivers/bus/pci/rte_bus_pci.h index b193114fe5..76cbf49ab8 100644 --- a/drivers/bus/pci/rte_bus_pci.h +++ b/drivers/bus/pci/rte_bus_pci.h @@ -101,6 +101,20 @@ off_t rte_pci_find_ext_capability(struct rte_pci_device *dev, uint32_t cap); __rte_experimental int rte_pci_set_bus_master(struct rte_pci_device *dev, bool enable); +/** + * Enable/Disable PASID (Process Address Space ID). + * + * @param dev + * A pointer to a rte_pci_device structure. + * @param offset + * Offset of the PASID external capability. + * @param enable + * Flag to enable or disable PASID. + */ +__rte_internal +int rte_pci_pasid_set_state(const struct rte_pci_device *dev, + off_t offset, bool enable); + /** * Read PCI config space. * diff --git a/drivers/bus/pci/version.map b/drivers/bus/pci/version.map index 161ab86d3b..f262af3316 100644 --- a/drivers/bus/pci/version.map +++ b/drivers/bus/pci/version.map @@ -27,6 +27,7 @@ INTERNAL { global: rte_pci_get_sysfs_path; + rte_pci_pasid_set_state; rte_pci_register; rte_pci_unregister; }; diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h index aab761b918..9876c3fb9d 100644 --- a/lib/pci/rte_pci.h +++ b/lib/pci/rte_pci.h @@ -45,6 +45,7 @@ extern "C" { #define RTE_PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */ #define RTE_PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ #define RTE_PCI_EXT_CAP_ID_SRIOV 0x10 /* SR-IOV*/ +#define RTE_PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */ /* Single Root I/O Virtualization */ #define RTE_PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ @@ -58,6 +59,9 @@ extern "C" { #define RTE_PCI_SRIOV_VF_DID 0x1a /* VF Device ID */ #define RTE_PCI_SRIOV_SUP_PGSIZE 0x1c /* Supported Page Sizes */ + +/* Process Address Space ID (RTE_PCI_EXT_CAP_ID_PASID) */ +#define RTE_PCI_PASID_CTRL 0x06 /* PASID control register */ /** Formatting string for PCI device identifier: Ex: 0000:00:01.0 */ #define PCI_PRI_FMT "%.4" PRIx32 ":%.2" PRIx8 ":%.2" PRIx8 ".%" PRIx8 #define PCI_PRI_STR_SIZE sizeof("XXXXXXXX:XX:XX.X") -- 2.25.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2023-12-11 17:56:25.219632200 +0800 +++ 0065-bus-pci-add-PASID-control.patch 2023-12-11 17:56:23.067652300 +0800 @@ -1 +1 @@ -From 60ea19609aecbd644d7ad7cb86ae06dd76291cf9 Mon Sep 17 00:00:00 2001 +From 5586a7be436c18b55d006ad4c21cca5ef403eb91 Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Xueming Li + +[ upstream commit 60ea19609aecbd644d7ad7cb86ae06dd76291cf9 ] @@ -16,2 +18,0 @@ -Cc: stable@dpdk.org - @@ -27 +28 @@ -index 921d957bf6..ba5e280d33 100644 +index e83d77090b..756e308fdf 100644 @@ -30 +31 @@ -@@ -938,6 +938,16 @@ rte_pci_set_bus_master(const struct rte_pci_device *dev, bool enable) +@@ -884,6 +884,16 @@ rte_pci_set_bus_master(struct rte_pci_device *dev, bool enable) @@ -48 +49 @@ -index 21e234abf0..f07bf9b588 100644 +index b193114fe5..76cbf49ab8 100644 @@ -51 +52 @@ -@@ -155,6 +155,20 @@ off_t rte_pci_find_ext_capability(const struct rte_pci_device *dev, uint32_t cap +@@ -101,6 +101,20 @@ off_t rte_pci_find_ext_capability(struct rte_pci_device *dev, uint32_t cap); @@ -53 +54 @@ - int rte_pci_set_bus_master(const struct rte_pci_device *dev, bool enable); + int rte_pci_set_bus_master(struct rte_pci_device *dev, bool enable); @@ -73 +74 @@ -index 74c5b075d5..9e4d8f5e54 100644 +index 161ab86d3b..f262af3316 100644 @@ -76 +77 @@ -@@ -36,6 +36,7 @@ INTERNAL { +@@ -27,6 +27,7 @@ INTERNAL { @@ -85 +86 @@ -index 69e932d910..0d2d8d8fed 100644 +index aab761b918..9876c3fb9d 100644 @@ -88,4 +89,4 @@ -@@ -101,6 +101,7 @@ extern "C" { - #define RTE_PCI_EXT_CAP_ID_ACS 0x0d /* Access Control Services */ - #define RTE_PCI_EXT_CAP_ID_SRIOV 0x10 /* SR-IOV */ - #define RTE_PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */ +@@ -45,6 +45,7 @@ extern "C" { + #define RTE_PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */ + #define RTE_PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */ + #define RTE_PCI_EXT_CAP_ID_SRIOV 0x10 /* SR-IOV*/ @@ -94,5 +95,5 @@ - /* Advanced Error Reporting (RTE_PCI_EXT_CAP_ID_ERR) */ - #define RTE_PCI_ERR_UNCOR_STATUS 0x04 /* Uncorrectable Error Status */ -@@ -133,6 +134,9 @@ extern "C" { - #define RTE_PCI_PRI_CTRL_ENABLE 0x0001 /* Enable */ - #define RTE_PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */ + /* Single Root I/O Virtualization */ + #define RTE_PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */ +@@ -58,6 +59,9 @@ extern "C" { + #define RTE_PCI_SRIOV_VF_DID 0x1a /* VF Device ID */ + #define RTE_PCI_SRIOV_SUP_PGSIZE 0x1c /* Supported Page Sizes */ @@ -99,0 +101 @@ ++ @@ -102 +103,0 @@ -+