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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BL6PEPF0001AB72.mail.protection.outlook.com (10.167.242.165) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7452.22 via Frontend Transport; Fri, 19 Apr 2024 13:10:49 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 19 Apr 2024 06:10:27 -0700 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 19 Apr 2024 06:10:25 -0700 From: Dariusz Sosnowski To: Luca Boccassi , Matan Azrad , Viacheslav Ovsiienko , Bing Zhao , Ori Kam CC: Subject: [PATCH 22.11] net/mlx5: fix incorrect counter cache dereference Date: Fri, 19 Apr 2024 15:09:49 +0200 Message-ID: <20240419130949.55341-1-dsosnowski@nvidia.com> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB72:EE_|DS7PR12MB9042:EE_ X-MS-Office365-Filtering-Correlation-Id: 59e4f610-677f-460e-7e1b-08dc6072223b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Apr 2024 13:10:49.4599 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 59e4f610-677f-460e-7e1b-08dc6072223b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB72.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB9042 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org When counter pool is prepopulated with preallocated counters, some counters were preloaded to per-queue caches. Per-queue counter cache can be disabled due to a change introduced in commit 244dbbf77871 ("net/mlx5: fix flow counter cache starvation"). Aforementioned preload happened even if counter cache was disabled, which caused a segmentation fault on the attempt to access the cache. This patch adds a missing check for counter cache before preloading. Fixes: 244dbbf77871 ("net/mlx5: fix flow counter cache starvation") Signed-off-by: Dariusz Sosnowski Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_hws_cnt.c | 38 ++++++++++++++++++--------------- 1 file changed, 21 insertions(+), 17 deletions(-) diff --git a/drivers/net/mlx5/mlx5_hws_cnt.c b/drivers/net/mlx5/mlx5_hws_cnt.c index 885effe3a1..d4ef44d1a3 100644 --- a/drivers/net/mlx5/mlx5_hws_cnt.c +++ b/drivers/net/mlx5/mlx5_hws_cnt.c @@ -25,28 +25,32 @@ static void __hws_cnt_id_load(struct mlx5_hws_cnt_pool *cpool) { uint32_t preload; - uint32_t q_num = cpool->cache->q_num; + uint32_t q_num; uint32_t cnt_num = mlx5_hws_cnt_pool_get_size(cpool); cnt_id_t cnt_id; uint32_t qidx, iidx = 0; struct rte_ring *qcache = NULL; - /* - * Counter ID order is important for tracking the max number of in used - * counter for querying, which means counter internal index order must - * be from zero to the number user configured, i.e: 0 - 8000000. - * Need to load counter ID in this order into the cache firstly, - * and then the global free list. - * In the end, user fetch the counter from minimal to the maximum. - */ - preload = RTE_MIN(cpool->cache->preload_sz, cnt_num / q_num); - for (qidx = 0; qidx < q_num; qidx++) { - for (; iidx < preload * (qidx + 1); iidx++) { - cnt_id = mlx5_hws_cnt_id_gen(cpool, iidx); - qcache = cpool->cache->qcache[qidx]; - if (qcache) - rte_ring_enqueue_elem(qcache, &cnt_id, - sizeof(cnt_id)); + /* If counter cache was disabled, only free list must prepopulated. */ + if (cpool->cache != NULL) { + q_num = cpool->cache->q_num; + /* + * Counter ID order is important for tracking the max number of in used + * counter for querying, which means counter internal index order must + * be from zero to the number user configured, i.e: 0 - 8000000. + * Need to load counter ID in this order into the cache firstly, + * and then the global free list. + * In the end, user fetch the counter from minimal to the maximum. + */ + preload = RTE_MIN(cpool->cache->preload_sz, cnt_num / q_num); + for (qidx = 0; qidx < q_num; qidx++) { + for (; iidx < preload * (qidx + 1); iidx++) { + cnt_id = mlx5_hws_cnt_id_gen(cpool, iidx); + qcache = cpool->cache->qcache[qidx]; + if (qcache) + rte_ring_enqueue_elem(qcache, &cnt_id, + sizeof(cnt_id)); + } } } for (; iidx < cnt_num; iidx++) { -- 2.39.2