From: Venkat Kumar Ande <venkatkumar.ande@amd.com>
To: <dev@dpdk.org>
Cc: <Selwin.Sebastian@amd.com>,
Venkat Kumar Ande <VenkatKumar.Ande@amd.com>, <stable@dpdk.org>,
Selwin Sebastian <selwin.sebastian@amd.com>
Subject: [PATCH v3 07/25] net/axgbe: enable PLL control for fixed PHY modes only
Date: Tue, 4 Jun 2024 17:41:39 +0530 [thread overview]
Message-ID: <20240604121157.3052-7-venkatkumar.ande@amd.com> (raw)
In-Reply-To: <20240604121157.3052-1-venkatkumar.ande@amd.com>
From: Venkat Kumar Ande <VenkatKumar.Ande@amd.com>
PLL control setting(RRC) is needed only in fixed PHY configuration to
fix the peer-peer issues. Without the PLL control setting, the link up
takes longer time in a fixed phy configuration.
Without the fix the user will not get the link come UP.
Driver implements SW RRC for Autoneg On configuration, hence PLL control
setting (RRC) is not needed for AN On configuration, and can be skipped.
Also, PLL re-initialization is not needed for PHY Power Off and RRC
commands. Otherwise, they lead to mailbox errors. Added the changes
accordingly.
Fixes: 09b0a36cc7ae ("net/axgbe: toggle PLL settings during rate change")
Cc: stable@dpdk.org
Signed-off-by: Venkat Kumar Ande <VenkatKumar.Ande@amd.com>
Acked-by: Selwin Sebastian <selwin.sebastian@amd.com>
---
drivers/net/axgbe/axgbe_phy_impl.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/net/axgbe/axgbe_phy_impl.c b/drivers/net/axgbe/axgbe_phy_impl.c
index f51830f800..bcefbf28f2 100644
--- a/drivers/net/axgbe/axgbe_phy_impl.c
+++ b/drivers/net/axgbe/axgbe_phy_impl.c
@@ -1228,6 +1228,10 @@ static void axgbe_phy_rx_reset(struct axgbe_port *pdata)
static void axgbe_phy_pll_ctrl(struct axgbe_port *pdata, bool enable)
{
+ /* PLL_CTRL feature needs to be enabled for fixed PHY modes (Non-Autoneg) only */
+ if (pdata->phy.autoneg != AUTONEG_DISABLE)
+ return;
+
XMDIO_WRITE_BITS(pdata, MDIO_MMD_PMAPMD, MDIO_VEND2_PMA_MISC_CTRL0,
XGBE_PMA_PLL_CTRL_MASK,
enable ? XGBE_PMA_PLL_CTRL_SET
@@ -1272,8 +1276,9 @@ static void axgbe_phy_perform_ratechange(struct axgbe_port *pdata,
axgbe_phy_rx_reset(pdata);
reenable_pll:
- /* Re-enable the PLL control */
- axgbe_phy_pll_ctrl(pdata, true);
+ /* Enable PLL re-initialization, not needed for PHY Power Off and RRC cmds */
+ if (cmd != 0 && cmd != 5)
+ axgbe_phy_pll_ctrl(pdata, true);
PMD_DRV_LOG(NOTICE, "firmware mailbox command did not complete\n");
}
--
2.34.1
next prev parent reply other threads:[~2024-06-04 12:12 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20240507124305.2318-1-VenkatKumar.Ande@amd.com>
2024-06-04 12:11 ` [PATCH v3 01/25] net/axgbe: fix mdio access for non-zero ports and CL45 PHYs Venkat Kumar Ande
2024-06-04 12:11 ` [PATCH v3 02/25] net/axgbe: reset link when the link never comes back Venkat Kumar Ande
2024-06-04 12:11 ` [PATCH v3 03/25] net/axgbe: fix fluctuations for 1G BELFUSE SFP Venkat Kumar Ande
2024-06-04 12:11 ` [PATCH v3 04/25] net/axgbe: update DMA coherency values Venkat Kumar Ande
2024-06-04 12:11 ` [PATCH v3 05/25] net/axgbe: disable interrupts during device removal Venkat Kumar Ande
2024-06-04 12:11 ` [PATCH v3 06/25] net/axgbe: yellow carp devices do not need rrc Venkat Kumar Ande
2024-06-04 12:11 ` Venkat Kumar Ande [this message]
2024-06-04 12:11 ` [PATCH v3 08/25] net/axgbe: fix the SFP codes check for DAC cables Venkat Kumar Ande
2024-06-04 12:11 ` [PATCH v3 09/25] net/axgbe: fix logic around active and passive cables Venkat Kumar Ande
2024-06-04 12:11 ` [PATCH v3 10/25] net/axgbe: check only the minimum speed for cables Venkat Kumar Ande
2024-06-04 12:11 ` [PATCH v3 11/25] net/axgbe: flow Tx Ctrl Registers are h/w version dependent Venkat Kumar Ande
2024-06-04 12:11 ` [PATCH v3 12/25] net/axgbe: delay AN timeout during KR training Venkat Kumar Ande
2024-06-04 12:11 ` [PATCH v3 13/25] net/axgbe: fix the false linkup in axgbe PHY status Venkat Kumar Ande
2024-06-05 17:07 ` [PATCH v3 01/25] net/axgbe: fix mdio access for non-zero ports and CL45 PHYs Ferruh Yigit
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