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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CH1PEPF0000A34A.mail.protection.outlook.com (10.167.244.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7762.17 via Frontend Transport; Fri, 12 Jul 2024 10:46:03 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 12 Jul 2024 03:45:47 -0700 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 12 Jul 2024 03:45:44 -0700 From: Xueming Li To: David Marchand CC: Bruce Richardson , Patrick Robb , Thomas Monjalon , dpdk stable Subject: patch 'bus/pci: fix build with musl 1.2.4 / Alpine 3.19' has been queued to stable release 23.11.2 Date: Fri, 12 Jul 2024 18:43:47 +0800 Message-ID: <20240712104528.308638-2-xuemingl@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240712104528.308638-1-xuemingl@nvidia.com> References: <20240712104528.308638-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000A34A:EE_|SJ0PR12MB7084:EE_ X-MS-Office365-Filtering-Correlation-Id: e52cc208-0314-4774-d9f0-08dca25fd381 X-LD-Processed: 43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(376014)(36860700013)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Jul 2024 10:46:03.2300 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e52cc208-0314-4774-d9f0-08dca25fd381 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000A34A.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB7084 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 23.11.2 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 07/14/24. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://git.dpdk.org/dpdk-stable/log/?h=23.11-staging This queued commit can be viewed at: https://git.dpdk.org/dpdk-stable/commit/?h=23.11-staging&id=338632b6637bda222734b6f33900709bb25c5f28 Thanks. Xueming Li --- >From 338632b6637bda222734b6f33900709bb25c5f28 Mon Sep 17 00:00:00 2001 From: David Marchand Date: Mon, 29 Apr 2024 12:00:59 +0200 Subject: [PATCH] bus/pci: fix build with musl 1.2.4 / Alpine 3.19 Cc: Xueming Li [ upstream commit 884f83ccf74b5364430d3b21c653d5f6e359e091 ] Following an upgrade of musl, pread64/pwrite64 wrappers are not provided anymore. Switch to POSIX pread/pwrite. Bugzilla ID: 1422 Signed-off-by: David Marchand Acked-by: Bruce Richardson Tested-by: Patrick Robb Tested-by: Thomas Monjalon --- drivers/bus/pci/linux/pci_vfio.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/bus/pci/linux/pci_vfio.c b/drivers/bus/pci/linux/pci_vfio.c index 3f3201daf2..baa0b9d9b3 100644 --- a/drivers/bus/pci/linux/pci_vfio.c +++ b/drivers/bus/pci/linux/pci_vfio.c @@ -80,7 +80,7 @@ pci_vfio_read_config(const struct rte_pci_device *dev, if ((uint64_t)len + offs > size) return -1; - return pread64(fd, buf, len, offset + offs); + return pread(fd, buf, len, offset + offs); } int @@ -101,7 +101,7 @@ pci_vfio_write_config(const struct rte_pci_device *dev, if ((uint64_t)len + offs > size) return -1; - return pwrite64(fd, buf, len, offset + offs); + return pwrite(fd, buf, len, offset + offs); } /* get PCI BAR number where MSI-X interrupts are */ @@ -155,7 +155,7 @@ pci_vfio_enable_bus_memory(struct rte_pci_device *dev, int dev_fd) return -1; } - ret = pread64(dev_fd, &cmd, sizeof(cmd), offset + RTE_PCI_COMMAND); + ret = pread(dev_fd, &cmd, sizeof(cmd), offset + RTE_PCI_COMMAND); if (ret != sizeof(cmd)) { RTE_LOG(ERR, EAL, "Cannot read command from PCI config space!\n"); @@ -166,7 +166,7 @@ pci_vfio_enable_bus_memory(struct rte_pci_device *dev, int dev_fd) return 0; cmd |= RTE_PCI_COMMAND_MEMORY; - ret = pwrite64(dev_fd, &cmd, sizeof(cmd), offset + RTE_PCI_COMMAND); + ret = pwrite(dev_fd, &cmd, sizeof(cmd), offset + RTE_PCI_COMMAND); if (ret != sizeof(cmd)) { RTE_LOG(ERR, EAL, "Cannot write command to PCI config space!\n"); @@ -425,7 +425,7 @@ pci_vfio_is_ioport_bar(const struct rte_pci_device *dev, int vfio_dev_fd, return -1; } - ret = pread64(vfio_dev_fd, &ioport_bar, sizeof(ioport_bar), + ret = pread(vfio_dev_fd, &ioport_bar, sizeof(ioport_bar), offset + RTE_PCI_BASE_ADDRESS_0 + bar_index * 4); if (ret != sizeof(ioport_bar)) { RTE_LOG(ERR, EAL, "Cannot read command (%x) from config space!\n", @@ -1250,7 +1250,7 @@ pci_vfio_ioport_read(struct rte_pci_ioport *p, if (vfio_dev_fd < 0) return; - if (pread64(vfio_dev_fd, data, + if (pread(vfio_dev_fd, data, len, p->base + offset) <= 0) RTE_LOG(ERR, EAL, "Can't read from PCI bar (%" PRIu64 ") : offset (%x)\n", @@ -1267,7 +1267,7 @@ pci_vfio_ioport_write(struct rte_pci_ioport *p, if (vfio_dev_fd < 0) return; - if (pwrite64(vfio_dev_fd, data, + if (pwrite(vfio_dev_fd, data, len, p->base + offset) <= 0) RTE_LOG(ERR, EAL, "Can't write to PCI bar (%" PRIu64 ") : offset (%x)\n", @@ -1298,7 +1298,7 @@ pci_vfio_mmio_read(const struct rte_pci_device *dev, int bar, if ((uint64_t)len + offs > size) return -1; - return pread64(fd, buf, len, offset + offs); + return pread(fd, buf, len, offset + offs); } int @@ -1318,7 +1318,7 @@ pci_vfio_mmio_write(const struct rte_pci_device *dev, int bar, if ((uint64_t)len + offs > size) return -1; - return pwrite64(fd, buf, len, offset + offs); + return pwrite(fd, buf, len, offset + offs); } int -- 2.34.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2024-07-12 18:40:14.456876585 +0800 +++ 0001-bus-pci-fix-build-with-musl-1.2.4-Alpine-3.19.patch 2024-07-12 18:40:13.896594252 +0800 @@ -1 +1 @@ -From 884f83ccf74b5364430d3b21c653d5f6e359e091 Mon Sep 17 00:00:00 2001 +From 338632b6637bda222734b6f33900709bb25c5f28 Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Xueming Li + +[ upstream commit 884f83ccf74b5364430d3b21c653d5f6e359e091 ] @@ -10 +12,0 @@ -Cc: stable@dpdk.org @@ -21 +23 @@ -index 87c16e6603..05b03a9667 100644 +index 3f3201daf2..baa0b9d9b3 100644 @@ -69 +71 @@ -@@ -1276,7 +1276,7 @@ pci_vfio_ioport_read(struct rte_pci_ioport *p, +@@ -1250,7 +1250,7 @@ pci_vfio_ioport_read(struct rte_pci_ioport *p, @@ -78 +80 @@ -@@ -1293,7 +1293,7 @@ pci_vfio_ioport_write(struct rte_pci_ioport *p, +@@ -1267,7 +1267,7 @@ pci_vfio_ioport_write(struct rte_pci_ioport *p, @@ -87 +89 @@ -@@ -1324,7 +1324,7 @@ pci_vfio_mmio_read(const struct rte_pci_device *dev, int bar, +@@ -1298,7 +1298,7 @@ pci_vfio_mmio_read(const struct rte_pci_device *dev, int bar, @@ -96 +98 @@ -@@ -1344,7 +1344,7 @@ pci_vfio_mmio_write(const struct rte_pci_device *dev, int bar, +@@ -1318,7 +1318,7 @@ pci_vfio_mmio_write(const struct rte_pci_device *dev, int bar,