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From: Maayan Kashani <mkashani@nvidia.com>
To: <dev@dpdk.org>
CC: <mkashani@nvidia.com>, <rasland@nvidia.com>, <stable@dpdk.org>, "Dariusz
Sosnowski" <dsosnowski@nvidia.com>, Viacheslav Ovsiienko
<viacheslavo@nvidia.com>, Bing Zhao <bingz@nvidia.com>, Ori Kam
<orika@nvidia.com>, Suanming Mou <suanmingm@nvidia.com>, Matan Azrad
<matan@nvidia.com>, Alex Vesker <valex@nvidia.com>
Subject: [PATCH v2] doc: document mlx5 HWS actions order
Date: Wed, 24 Jul 2024 10:36:16 +0300
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Add actions order supported in mlx5 PMD when HW steering flow engine
is used.
This limitation existed since HW Steering flow engine was introduced.
Fixes: 22681deead3e ("net/mlx5/hws: enable hardware steering")
Cc: stable@dpdk.org
Signed-off-by: Maayan Kashani <mkashani@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
---
doc/guides/nics/mlx5.rst | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index 43fc181d8dc..4c00bb7755c 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -251,6 +251,26 @@ Limitations
IPv6 routing extension matching is not supported in flow template relaxed
matching mode (see ``struct rte_flow_pattern_template_attr::relaxed_matching``).
+ - The supported actions order is as below::
+
+ MARK(a)
+ *_DECAP(b)
+ OF_POP_VLAN
+ COUNT | AGE
+ METER_MARK | CONNTRACK
+ OF_PUSH_VLAN
+ MODIFY_FIELD
+ *_ENCAP(c)
+ JUMP | DROP | RSS(a) | QUEUE(a) | REPRESENTED_PORT(d)
+
+ a. Only supported on ingress.
+ b. Any decapsulation action, including the combination of RAW_ENCAP and RAW_DECAP actions
+ which results in L3 decapsulation.
+ Not supported on egress.
+ c. Any encapsulation action, including the combination of RAW_ENCAP and RAW_DECAP actions
+ which results in L3 encap.
+ d. Only in transfer (switchdev) mode.
+
- When using Verbs flow engine (``dv_flow_en`` = 0), flow pattern without any
specific VLAN will match for VLAN packets as well:
--
2.21.0