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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by SN1PEPF00026369.mail.protection.outlook.com (10.167.241.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7849.8 via Frontend Transport; Mon, 12 Aug 2024 13:02:58 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 12 Aug 2024 06:02:43 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 12 Aug 2024 06:02:41 -0700 From: Xueming Li To: Dariusz Sosnowski CC: , Viacheslav Ovsiienko , "dpdk stable" Subject: patch 'net/mlx5: fix disabling E-Switch default flow rules' has been queued to stable release 23.11.2 Date: Mon, 12 Aug 2024 20:50:05 +0800 Message-ID: <20240812125035.389667-129-xuemingl@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240812125035.389667-1-xuemingl@nvidia.com> References: <20240712110153.309690-23-xuemingl@nvidia.com> <20240812125035.389667-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00026369:EE_|DS0PR12MB7875:EE_ X-MS-Office365-Filtering-Correlation-Id: 2e4b34a7-9ad4-4240-5d74-08dcbacf1735 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(82310400026)(1800799024)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Aug 2024 13:02:58.8575 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2e4b34a7-9ad4-4240-5d74-08dcbacf1735 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00026369.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7875 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 23.11.2 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 08/14/24. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://git.dpdk.org/dpdk-stable/log/?h=23.11-staging This queued commit can be viewed at: https://git.dpdk.org/dpdk-stable/commit/?h=23.11-staging&id=6bf4a626e4810f6ed97c94a6c6c86a0a8bac0003 Thanks. Xueming Li --- >From 6bf4a626e4810f6ed97c94a6c6c86a0a8bac0003 Mon Sep 17 00:00:00 2001 From: Dariusz Sosnowski Date: Thu, 18 Jul 2024 11:57:15 +0200 Subject: [PATCH] net/mlx5: fix disabling E-Switch default flow rules Cc: Xueming Li [ upstream commit cf9a91c67b88071a03beb32a3ea9970e6ee00391 ] `fdb_def_rule_en` devarg controls whether mlx5 PMD creates default E-Switch flow rules for: - Transferring traffic from wire, VFs and SFs to group 1 (default jump). - Providing default behavior for application traffic (default SQ miss flow rules). With these flow rules, applications effectively create transfer flow rules in group 1 and higher (application group is translated to one higher) allowing for faster insertion on all groups and providing ability to forward to VF, SF and wire on any group. By default, these rules are created (`fdb_def_rule_en` == 1). When these default flow rules are disabled (`fdb_def_rule_en` == 0) with HW Steering flow engine (`dv_flow_en` == 2) only creation of default jump rules was disabled. Also, necessary template table and pattern/actions templates were created as well, but they were never used. SQ miss flow rules were still created. This is a bug, because with `fdb_def_rule_en` == 0, application should not expect any default E-Switch flow rules. This patch fixes that by disabling all default E-Switch flow rules creation and disabling creating templates for these flow rules, when `fdb_def_rule_en` == 0. If an application needs to run with these flow rules disabled, and requires flow rules providing SQ miss flow rules functionality, then application must explicitly create similar flow rules. Fixes: 1939eb6f660c ("net/mlx5: support flow port action with HWS") Signed-off-by: Dariusz Sosnowski Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_flow_hw.c | 142 ++++++++++++++++++-------------- drivers/net/mlx5/mlx5_trigger.c | 4 +- drivers/net/mlx5/mlx5_txq.c | 13 ++- 3 files changed, 91 insertions(+), 68 deletions(-) diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c index fa6ae623c9..af4df13b2f 100644 --- a/drivers/net/mlx5/mlx5_flow_hw.c +++ b/drivers/net/mlx5/mlx5_flow_hw.c @@ -8627,6 +8627,7 @@ flow_hw_create_ctrl_tables(struct rte_eth_dev *dev, struct rte_flow_error *error struct mlx5_flow_hw_ctrl_fdb *hw_ctrl_fdb; uint32_t xmeta = priv->sh->config.dv_xmeta_en; uint32_t repr_matching = priv->sh->config.repr_matching; + uint32_t fdb_def_rule = priv->sh->config.fdb_def_rule; MLX5_ASSERT(priv->hw_ctrl_fdb == NULL); hw_ctrl_fdb = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*hw_ctrl_fdb), 0, SOCKET_ID_ANY); @@ -8637,70 +8638,79 @@ flow_hw_create_ctrl_tables(struct rte_eth_dev *dev, struct rte_flow_error *error goto err; } priv->hw_ctrl_fdb = hw_ctrl_fdb; - /* Create templates and table for default SQ miss flow rules - root table. */ - hw_ctrl_fdb->esw_mgr_items_tmpl = flow_hw_create_ctrl_esw_mgr_pattern_template(dev, error); - if (!hw_ctrl_fdb->esw_mgr_items_tmpl) { - DRV_LOG(ERR, "port %u failed to create E-Switch Manager item" - " template for control flows", dev->data->port_id); - goto err; - } - hw_ctrl_fdb->regc_jump_actions_tmpl = flow_hw_create_ctrl_regc_jump_actions_template - (dev, error); - if (!hw_ctrl_fdb->regc_jump_actions_tmpl) { - DRV_LOG(ERR, "port %u failed to create REG_C set and jump action template" - " for control flows", dev->data->port_id); - goto err; - } - hw_ctrl_fdb->hw_esw_sq_miss_root_tbl = flow_hw_create_ctrl_sq_miss_root_table - (dev, hw_ctrl_fdb->esw_mgr_items_tmpl, hw_ctrl_fdb->regc_jump_actions_tmpl, - error); - if (!hw_ctrl_fdb->hw_esw_sq_miss_root_tbl) { - DRV_LOG(ERR, "port %u failed to create table for default sq miss (root table)" - " for control flows", dev->data->port_id); - goto err; - } - /* Create templates and table for default SQ miss flow rules - non-root table. */ - hw_ctrl_fdb->regc_sq_items_tmpl = flow_hw_create_ctrl_regc_sq_pattern_template(dev, error); - if (!hw_ctrl_fdb->regc_sq_items_tmpl) { - DRV_LOG(ERR, "port %u failed to create SQ item template for" - " control flows", dev->data->port_id); - goto err; - } - hw_ctrl_fdb->port_actions_tmpl = flow_hw_create_ctrl_port_actions_template(dev, error); - if (!hw_ctrl_fdb->port_actions_tmpl) { - DRV_LOG(ERR, "port %u failed to create port action template" - " for control flows", dev->data->port_id); - goto err; - } - hw_ctrl_fdb->hw_esw_sq_miss_tbl = flow_hw_create_ctrl_sq_miss_table - (dev, hw_ctrl_fdb->regc_sq_items_tmpl, hw_ctrl_fdb->port_actions_tmpl, - error); - if (!hw_ctrl_fdb->hw_esw_sq_miss_tbl) { - DRV_LOG(ERR, "port %u failed to create table for default sq miss (non-root table)" - " for control flows", dev->data->port_id); - goto err; - } - /* Create templates and table for default FDB jump flow rules. */ - hw_ctrl_fdb->port_items_tmpl = flow_hw_create_ctrl_port_pattern_template(dev, error); - if (!hw_ctrl_fdb->port_items_tmpl) { - DRV_LOG(ERR, "port %u failed to create SQ item template for" - " control flows", dev->data->port_id); - goto err; - } - hw_ctrl_fdb->jump_one_actions_tmpl = flow_hw_create_ctrl_jump_actions_template - (dev, MLX5_HW_LOWEST_USABLE_GROUP, error); - if (!hw_ctrl_fdb->jump_one_actions_tmpl) { - DRV_LOG(ERR, "port %u failed to create jump action template" - " for control flows", dev->data->port_id); - goto err; - } - hw_ctrl_fdb->hw_esw_zero_tbl = flow_hw_create_ctrl_jump_table - (dev, hw_ctrl_fdb->port_items_tmpl, hw_ctrl_fdb->jump_one_actions_tmpl, - error); - if (!hw_ctrl_fdb->hw_esw_zero_tbl) { - DRV_LOG(ERR, "port %u failed to create table for default jump to group 1" - " for control flows", dev->data->port_id); - goto err; + if (fdb_def_rule) { + /* Create templates and table for default SQ miss flow rules - root table. */ + hw_ctrl_fdb->esw_mgr_items_tmpl = + flow_hw_create_ctrl_esw_mgr_pattern_template(dev, error); + if (!hw_ctrl_fdb->esw_mgr_items_tmpl) { + DRV_LOG(ERR, "port %u failed to create E-Switch Manager item" + " template for control flows", dev->data->port_id); + goto err; + } + hw_ctrl_fdb->regc_jump_actions_tmpl = + flow_hw_create_ctrl_regc_jump_actions_template(dev, error); + if (!hw_ctrl_fdb->regc_jump_actions_tmpl) { + DRV_LOG(ERR, "port %u failed to create REG_C set and jump action template" + " for control flows", dev->data->port_id); + goto err; + } + hw_ctrl_fdb->hw_esw_sq_miss_root_tbl = + flow_hw_create_ctrl_sq_miss_root_table + (dev, hw_ctrl_fdb->esw_mgr_items_tmpl, + hw_ctrl_fdb->regc_jump_actions_tmpl, error); + if (!hw_ctrl_fdb->hw_esw_sq_miss_root_tbl) { + DRV_LOG(ERR, "port %u failed to create table for default sq miss (root table)" + " for control flows", dev->data->port_id); + goto err; + } + /* Create templates and table for default SQ miss flow rules - non-root table. */ + hw_ctrl_fdb->regc_sq_items_tmpl = + flow_hw_create_ctrl_regc_sq_pattern_template(dev, error); + if (!hw_ctrl_fdb->regc_sq_items_tmpl) { + DRV_LOG(ERR, "port %u failed to create SQ item template for" + " control flows", dev->data->port_id); + goto err; + } + hw_ctrl_fdb->port_actions_tmpl = + flow_hw_create_ctrl_port_actions_template(dev, error); + if (!hw_ctrl_fdb->port_actions_tmpl) { + DRV_LOG(ERR, "port %u failed to create port action template" + " for control flows", dev->data->port_id); + goto err; + } + hw_ctrl_fdb->hw_esw_sq_miss_tbl = + flow_hw_create_ctrl_sq_miss_table + (dev, hw_ctrl_fdb->regc_sq_items_tmpl, + hw_ctrl_fdb->port_actions_tmpl, error); + if (!hw_ctrl_fdb->hw_esw_sq_miss_tbl) { + DRV_LOG(ERR, "port %u failed to create table for default sq miss (non-root table)" + " for control flows", dev->data->port_id); + goto err; + } + /* Create templates and table for default FDB jump flow rules. */ + hw_ctrl_fdb->port_items_tmpl = + flow_hw_create_ctrl_port_pattern_template(dev, error); + if (!hw_ctrl_fdb->port_items_tmpl) { + DRV_LOG(ERR, "port %u failed to create SQ item template for" + " control flows", dev->data->port_id); + goto err; + } + hw_ctrl_fdb->jump_one_actions_tmpl = + flow_hw_create_ctrl_jump_actions_template + (dev, MLX5_HW_LOWEST_USABLE_GROUP, error); + if (!hw_ctrl_fdb->jump_one_actions_tmpl) { + DRV_LOG(ERR, "port %u failed to create jump action template" + " for control flows", dev->data->port_id); + goto err; + } + hw_ctrl_fdb->hw_esw_zero_tbl = flow_hw_create_ctrl_jump_table + (dev, hw_ctrl_fdb->port_items_tmpl, + hw_ctrl_fdb->jump_one_actions_tmpl, error); + if (!hw_ctrl_fdb->hw_esw_zero_tbl) { + DRV_LOG(ERR, "port %u failed to create table for default jump to group 1" + " for control flows", dev->data->port_id); + goto err; + } } /* Create templates and table for default Tx metadata copy flow rule. */ if (!repr_matching && xmeta == MLX5_XMETA_MODE_META32_HWS) { @@ -12234,6 +12244,8 @@ mlx5_flow_hw_esw_destroy_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn) } proxy_dev = &rte_eth_devices[proxy_port_id]; proxy_priv = proxy_dev->data->dev_private; + /* FDB default flow rules must be enabled. */ + MLX5_ASSERT(proxy_priv->sh->config.fdb_def_rule); if (!proxy_priv->dr_ctx) return 0; if (!proxy_priv->hw_ctrl_fdb || @@ -12298,6 +12310,8 @@ mlx5_flow_hw_esw_create_default_jump_flow(struct rte_eth_dev *dev) } proxy_dev = &rte_eth_devices[proxy_port_id]; proxy_priv = proxy_dev->data->dev_private; + /* FDB default flow rules must be enabled. */ + MLX5_ASSERT(proxy_priv->sh->config.fdb_def_rule); if (!proxy_priv->dr_ctx) { DRV_LOG(DEBUG, "Transfer proxy port (port %u) of port %u must be configured " "for HWS to create default FDB jump rule. Default rule will " diff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c index f8d67282ce..fe2c512c5c 100644 --- a/drivers/net/mlx5/mlx5_trigger.c +++ b/drivers/net/mlx5/mlx5_trigger.c @@ -1498,7 +1498,9 @@ mlx5_traffic_enable_hws(struct rte_eth_dev *dev) if (!txq) continue; queue = mlx5_txq_get_sqn(txq); - if ((priv->representor || priv->master) && config->dv_esw_en) { + if ((priv->representor || priv->master) && + config->dv_esw_en && + config->fdb_def_rule) { if (mlx5_flow_hw_esw_create_sq_miss_flow(dev, queue, false)) { mlx5_txq_release(dev, i); goto error; diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c index 1ac43548b2..aac078a6ed 100644 --- a/drivers/net/mlx5/mlx5_txq.c +++ b/drivers/net/mlx5/mlx5_txq.c @@ -1311,11 +1311,18 @@ rte_pmd_mlx5_external_sq_enable(uint16_t port_id, uint32_t sq_num) } #ifdef HAVE_MLX5_HWS_SUPPORT if (priv->sh->config.dv_flow_en == 2) { - if (mlx5_flow_hw_esw_create_sq_miss_flow(dev, sq_num, true)) - return -rte_errno; + bool sq_miss_created = false; + + if (priv->sh->config.fdb_def_rule) { + if (mlx5_flow_hw_esw_create_sq_miss_flow(dev, sq_num, true)) + return -rte_errno; + sq_miss_created = true; + } + if (priv->sh->config.repr_matching && mlx5_flow_hw_tx_repr_matching_flow(dev, sq_num, true)) { - mlx5_flow_hw_esw_destroy_sq_miss_flow(dev, sq_num); + if (sq_miss_created) + mlx5_flow_hw_esw_destroy_sq_miss_flow(dev, sq_num); return -rte_errno; } return 0; -- 2.34.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2024-08-12 20:44:06.554055678 +0800 +++ 0128-net-mlx5-fix-disabling-E-Switch-default-flow-rules.patch 2024-08-12 20:44:02.515069377 +0800 @@ -1 +1 @@ -From cf9a91c67b88071a03beb32a3ea9970e6ee00391 Mon Sep 17 00:00:00 2001 +From 6bf4a626e4810f6ed97c94a6c6c86a0a8bac0003 Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Xueming Li + +[ upstream commit cf9a91c67b88071a03beb32a3ea9970e6ee00391 ] @@ -37 +39,0 @@ -Cc: stable@dpdk.org @@ -48 +50 @@ -index e7d8c251a0..fe7df7305f 100644 +index fa6ae623c9..af4df13b2f 100644 @@ -51 +53 @@ -@@ -10580,6 +10580,7 @@ flow_hw_create_ctrl_tables(struct rte_eth_dev *dev, struct rte_flow_error *error +@@ -8627,6 +8627,7 @@ flow_hw_create_ctrl_tables(struct rte_eth_dev *dev, struct rte_flow_error *error @@ -59 +61 @@ -@@ -10590,70 +10591,79 @@ flow_hw_create_ctrl_tables(struct rte_eth_dev *dev, struct rte_flow_error *error +@@ -8637,70 +8638,79 @@ flow_hw_create_ctrl_tables(struct rte_eth_dev *dev, struct rte_flow_error *error @@ -203 +205 @@ -@@ -15383,6 +15393,8 @@ mlx5_flow_hw_esw_destroy_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn) +@@ -12234,6 +12244,8 @@ mlx5_flow_hw_esw_destroy_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sqn) @@ -212 +214 @@ -@@ -15447,6 +15459,8 @@ mlx5_flow_hw_esw_create_default_jump_flow(struct rte_eth_dev *dev) +@@ -12298,6 +12310,8 @@ mlx5_flow_hw_esw_create_default_jump_flow(struct rte_eth_dev *dev) @@ -222 +224 @@ -index 6fa7c01cd0..a65a460731 100644 +index f8d67282ce..fe2c512c5c 100644 @@ -225 +227 @@ -@@ -1504,7 +1504,9 @@ mlx5_traffic_enable_hws(struct rte_eth_dev *dev) +@@ -1498,7 +1498,9 @@ mlx5_traffic_enable_hws(struct rte_eth_dev *dev) @@ -237 +239 @@ -index 8eb1ae1f03..f05534e168 100644 +index 1ac43548b2..aac078a6ed 100644 @@ -240 +242 @@ -@@ -1363,11 +1363,18 @@ rte_pmd_mlx5_external_sq_enable(uint16_t port_id, uint32_t sq_num) +@@ -1311,11 +1311,18 @@ rte_pmd_mlx5_external_sq_enable(uint16_t port_id, uint32_t sq_num)