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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by SN1PEPF0002636C.mail.protection.outlook.com (10.167.241.137) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7849.8 via Frontend Transport; Mon, 12 Aug 2024 13:03:02 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 12 Aug 2024 06:02:45 -0700 Received: from nvidia.com (10.126.230.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 12 Aug 2024 06:02:43 -0700 From: Xueming Li To: Chengwen Feng CC: , Jie Hai , dpdk stable Subject: patch 'net/hns3: check Rx DMA address alignmnent' has been queued to stable release 23.11.2 Date: Mon, 12 Aug 2024 20:50:06 +0800 Message-ID: <20240812125035.389667-130-xuemingl@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240812125035.389667-1-xuemingl@nvidia.com> References: <20240712110153.309690-23-xuemingl@nvidia.com> <20240812125035.389667-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.230.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636C:EE_|MN2PR12MB4143:EE_ X-MS-Office365-Filtering-Correlation-Id: f64bfd69-392f-4f4d-ca85-08dcbacf1922 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(376014)(82310400026)(36860700013); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Aug 2024 13:03:02.0912 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f64bfd69-392f-4f4d-ca85-08dcbacf1922 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4143 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 23.11.2 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 08/14/24. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://git.dpdk.org/dpdk-stable/log/?h=23.11-staging This queued commit can be viewed at: https://git.dpdk.org/dpdk-stable/commit/?h=23.11-staging&id=7deaec6ac8c2242b225cf97963cdd8b4dc176b69 Thanks. Xueming Li --- >From 7deaec6ac8c2242b225cf97963cdd8b4dc176b69 Mon Sep 17 00:00:00 2001 From: Chengwen Feng Date: Mon, 15 Jul 2024 10:04:39 +0800 Subject: [PATCH] net/hns3: check Rx DMA address alignmnent Cc: Xueming Li [ upstream commit d14c995b775a9b5910c51c3ab3685b320736f3f6 ] The network engine has Rx DMA address align requirement, if this requirement is violated, the Rx function will be abnormal. The detail requirement is: 1) For HIP08 platform, require 64-bytes alignment. 2) For later platform, require 128-bytes alignment. The setup Rx DMA address exists both on the control and data plane, to ensure performance, the alignment check is added only on the control plane. Fixes: bba636698316 ("net/hns3: support Rx/Tx and related operations") Signed-off-by: Chengwen Feng Signed-off-by: Jie Hai --- drivers/net/hns3/hns3_ethdev.c | 2 ++ drivers/net/hns3/hns3_ethdev.h | 8 ++++++++ drivers/net/hns3/hns3_ethdev_vf.c | 2 ++ drivers/net/hns3/hns3_rxtx.c | 21 +++++++++++++++++++++ 4 files changed, 33 insertions(+) diff --git a/drivers/net/hns3/hns3_ethdev.c b/drivers/net/hns3/hns3_ethdev.c index 90dbc4a84b..8e18aaf110 100644 --- a/drivers/net/hns3/hns3_ethdev.c +++ b/drivers/net/hns3/hns3_ethdev.c @@ -2738,6 +2738,7 @@ hns3_get_capability(struct hns3_hw *hw) hw->rss_info.ipv6_sctp_offload_supported = false; hw->udp_cksum_mode = HNS3_SPECIAL_PORT_SW_CKSUM_MODE; pf->support_multi_tc_pause = false; + hw->rx_dma_addr_align = HNS3_RX_DMA_ADDR_ALIGN_64; return 0; } @@ -2758,6 +2759,7 @@ hns3_get_capability(struct hns3_hw *hw) hw->rss_info.ipv6_sctp_offload_supported = true; hw->udp_cksum_mode = HNS3_SPECIAL_PORT_HW_CKSUM_MODE; pf->support_multi_tc_pause = true; + hw->rx_dma_addr_align = HNS3_RX_DMA_ADDR_ALIGN_128; return 0; } diff --git a/drivers/net/hns3/hns3_ethdev.h b/drivers/net/hns3/hns3_ethdev.h index e70c5fff2a..c190d5109b 100644 --- a/drivers/net/hns3/hns3_ethdev.h +++ b/drivers/net/hns3/hns3_ethdev.h @@ -487,6 +487,9 @@ struct hns3_queue_intr { #define HNS3_PKTS_DROP_STATS_MODE1 0 #define HNS3_PKTS_DROP_STATS_MODE2 1 +#define HNS3_RX_DMA_ADDR_ALIGN_128 128 +#define HNS3_RX_DMA_ADDR_ALIGN_64 64 + struct hns3_hw { struct rte_eth_dev_data *data; void *io_base; @@ -554,6 +557,11 @@ struct hns3_hw { * direction. */ uint8_t min_tx_pkt_len; + /* + * The required alignment of the DMA address of the RX buffer. + * See HNS3_RX_DMA_ADDR_ALIGN_XXX for available values. + */ + uint16_t rx_dma_addr_align; struct hns3_queue_intr intr; /* diff --git a/drivers/net/hns3/hns3_ethdev_vf.c b/drivers/net/hns3/hns3_ethdev_vf.c index 83d3d66005..d4d691ad86 100644 --- a/drivers/net/hns3/hns3_ethdev_vf.c +++ b/drivers/net/hns3/hns3_ethdev_vf.c @@ -707,6 +707,7 @@ hns3vf_get_capability(struct hns3_hw *hw) hw->min_tx_pkt_len = HNS3_HIP08_MIN_TX_PKT_LEN; hw->rss_info.ipv6_sctp_offload_supported = false; hw->promisc_mode = HNS3_UNLIMIT_PROMISC_MODE; + hw->rx_dma_addr_align = HNS3_RX_DMA_ADDR_ALIGN_64; return 0; } @@ -724,6 +725,7 @@ hns3vf_get_capability(struct hns3_hw *hw) hw->drop_stats_mode = HNS3_PKTS_DROP_STATS_MODE2; hw->rss_info.ipv6_sctp_offload_supported = true; hw->promisc_mode = HNS3_LIMIT_PROMISC_MODE; + hw->rx_dma_addr_align = HNS3_RX_DMA_ADDR_ALIGN_128; return 0; } diff --git a/drivers/net/hns3/hns3_rxtx.c b/drivers/net/hns3/hns3_rxtx.c index 75ea6bdca9..8d0db134d2 100644 --- a/drivers/net/hns3/hns3_rxtx.c +++ b/drivers/net/hns3/hns3_rxtx.c @@ -273,12 +273,27 @@ hns3_free_all_queues(struct rte_eth_dev *dev) hns3_free_tx_queues(dev); } +static int +hns3_check_rx_dma_addr(struct hns3_hw *hw, uint64_t dma_addr) +{ + uint64_t rem; + + rem = dma_addr & (hw->rx_dma_addr_align - 1); + if (rem > 0) { + hns3_err(hw, "The IO address of the beginning of the mbuf data " + "must be %u-byte aligned", hw->rx_dma_addr_align); + return -EINVAL; + } + return 0; +} + static int hns3_alloc_rx_queue_mbufs(struct hns3_hw *hw, struct hns3_rx_queue *rxq) { struct rte_mbuf *mbuf; uint64_t dma_addr; uint16_t i; + int ret; for (i = 0; i < rxq->nb_rx_desc; i++) { mbuf = rte_mbuf_raw_alloc(rxq->mb_pool); @@ -299,6 +314,12 @@ hns3_alloc_rx_queue_mbufs(struct hns3_hw *hw, struct hns3_rx_queue *rxq) dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf)); rxq->rx_ring[i].addr = dma_addr; rxq->rx_ring[i].rx.bd_base_info = 0; + + ret = hns3_check_rx_dma_addr(hw, dma_addr); + if (ret != 0) { + hns3_rx_queue_release_mbufs(rxq); + return ret; + } } return 0; -- 2.34.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2024-08-12 20:44:06.603907474 +0800 +++ 0129-net-hns3-check-Rx-DMA-address-alignmnent.patch 2024-08-12 20:44:02.525069379 +0800 @@ -1 +1 @@ -From d14c995b775a9b5910c51c3ab3685b320736f3f6 Mon Sep 17 00:00:00 2001 +From 7deaec6ac8c2242b225cf97963cdd8b4dc176b69 Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Xueming Li + +[ upstream commit d14c995b775a9b5910c51c3ab3685b320736f3f6 ] @@ -17 +19,0 @@ -Cc: stable@dpdk.org @@ -29 +31 @@ -index 327f6fe908..ec1251cb7e 100644 +index 90dbc4a84b..8e18aaf110 100644 @@ -49 +51 @@ -index a6b652455b..799b61038a 100644 +index e70c5fff2a..c190d5109b 100644 @@ -75 +77 @@ -index b83d5b9589..ea9225cd26 100644 +index 83d3d66005..d4d691ad86 100644 @@ -95 +97 @@ -index d7f9cff547..5941b966e0 100644 +index 75ea6bdca9..8d0db134d2 100644