From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id E3B43457A1 for ; Mon, 12 Aug 2024 15:05:54 +0200 (CEST) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id DC34E4065A; Mon, 12 Aug 2024 15:05:54 +0200 (CEST) Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2045.outbound.protection.outlook.com [40.107.220.45]) by mails.dpdk.org (Postfix) with ESMTP id B4D02402C3 for ; Mon, 12 Aug 2024 15:05:52 +0200 (CEST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Xq0bJjybN33LaTKpC2iNHMdIyLogqTgE0qBa+HtQnL9jlt0ysyDTFy7akoe38kwTt7TnEMdlSPaJFtCh9+v6+AMG5a8Q7gM6ImfD3jcS9X726kVuajd3tqiaRvVBhCOLEv0gYYwLYdbJ8/b1QoCNDc1Wi2M/saDwAOlYw5kEjPFaRaPwrmSzeiz1A9VCscwr2TfyGUZDU//JecDWuh0rtOzg/VtuQv2d0yJ9rKYprLPItWUbnoLAxtnqGeaeLriQ5GEL2Sr4ZcwNtUVItclpMYjhAg9ioEhrSCqdfiUutDfaWxJP6m9TikeYDYrDu/Dk0Pl13wnOuSh9hz6yoizi+Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=BhfOYloldTdjXxVwe0yJa8OdEfkPoNK/PpdWxWq2ijU=; b=kSmIWhdTrh9Vv6tPV2U6HMjy+IqTrIEgBFzePtVxosaLJx5ydr4JtkHSNlYHaiN0RhtZmLqCl6qtheZGdOqrhXHB040ciGsELNuPI8e6sZgoq9F3LYxTdHf6Bjk8k97nUy/Drn297wf+vp2yY+dPM95M5ICauUjg71kWcno8CqFRaTXXHFgPIc/t7oGj1Ow92Yd/An9ctgLe4H1BmGu68vWvb+4FS9H0A/yU1/G/8G3SPmYe9CzexXk++9jbAO7GZ43cd2zQXa2q+6g0AyRF59PWpixbBoMgrAJtobqOl31ZIdxQdWZiXFrHx5C3Cq88VpOrhE07sZfPTnxM5I82hQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=amd.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=BhfOYloldTdjXxVwe0yJa8OdEfkPoNK/PpdWxWq2ijU=; b=oHd/i52irYk0qGi7ftC1fSKacp7IDe3Cen0mDk4Sxu+x2nS+9vrnJGdurBn14wslo19OJ0+eb3kcLOB5KBkbShvFC6EiwKE73n7PYTGgxnsspN1XMQh/+1DAwper4QsyKfB+OK9ZAGw+s44lekJA3uQ/AWr+GlhH0W8ifZd2MrenjdyDuw21xcUmMFuilYLdab2XL0DnO9zsD9JB9zbqjbTWT30rC0C8LcVGK3Te7De4LXIrYYJN66daxl+lUyTIMgObb6BJn+VOf1SPTpBtqvesuNUaggX/BEbRHsObeKJsSBmcXjAYZp0sEs71R8gY7xW40HueVumelLvQYWr2tA== Received: from SA0PR11CA0011.namprd11.prod.outlook.com (2603:10b6:806:d3::16) by CY8PR12MB8412.namprd12.prod.outlook.com (2603:10b6:930:6f::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7849.20; Mon, 12 Aug 2024 13:05:49 +0000 Received: from SN1PEPF00026367.namprd02.prod.outlook.com (2603:10b6:806:d3:cafe::43) by SA0PR11CA0011.outlook.office365.com (2603:10b6:806:d3::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.33 via Frontend Transport; Mon, 12 Aug 2024 13:05:49 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by SN1PEPF00026367.mail.protection.outlook.com (10.167.241.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7849.8 via Frontend Transport; Mon, 12 Aug 2024 13:05:49 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 12 Aug 2024 06:05:31 -0700 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 12 Aug 2024 06:05:28 -0700 From: Xueming Li To: Sivaprasad Tummala CC: , Konstantin Ananyev , =?UTF-8?q?Morten=20Br=C3=B8rup?= , Ferruh Yigit , dpdk stable Subject: patch 'examples: fix lcore ID restriction' has been queued to stable release 23.11.2 Date: Mon, 12 Aug 2024 20:50:34 +0800 Message-ID: <20240812125035.389667-158-xuemingl@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240812125035.389667-1-xuemingl@nvidia.com> References: <20240712110153.309690-23-xuemingl@nvidia.com> <20240812125035.389667-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF00026367:EE_|CY8PR12MB8412:EE_ X-MS-Office365-Filtering-Correlation-Id: 98e14d46-96cb-4569-8131-08dcbacf7ccd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|36860700013|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?utf-8?B?cDFaMUNBVUdLSEhMNlB0dTlDVkZ2eHg2SXdVRGVJZnJiQlh1ZEVBNmppenIy?= =?utf-8?B?bGtmUXFRSzVpaHBJL3lGM0h5TS80elNEODZGQXZLem1VWVRoTm1YZllXUFla?= =?utf-8?B?R1FaRXdIY3NRWVEyWGlpRTk0OHo5aENESlZuNENEOUxPaXFYQTlNSEd6YjJa?= =?utf-8?B?QTB0UXNHNElkUEowRFVQUEhULzdjb1ZtUnFqUUpDM2tGSjdJbi9pT3I0UzFj?= =?utf-8?B?TXZnZnUxY1IwWDV0WWlDZGprQkNWNklYL1Q3WW1JNCtsUVA4bnBMTFBSU0Rr?= =?utf-8?B?dG4rOWJKYTRsODhveDBIcHltdTlSUFpPT0xuN3hYZHZnT1lTU1NYVFRBNytY?= =?utf-8?B?dWRXUEhWVmhGSlBabEluNWQrR2d1L3ozWnNMTmFQTG5MdTJBRC8vQlFObWNI?= =?utf-8?B?dVQ3OWFUdWt3OXRlWVhVSUJ3VytFQWZXbDFLK2l4SlVkQjhxUGRtaGF3a3FS?= =?utf-8?B?Q2FId2UwOHZ3cWtDay9EYUtSblJVUW1OWmJ3bkZVYnFGQ1AzNHg0YllYMUVW?= =?utf-8?B?dGx6WXJFVDkrQVExUEdPSnNaaG15R05IdU1GSjJka0RHQlgzMjE3TTVLc2ZX?= =?utf-8?B?blhVcDNEcDd4YnhzL3NxbU1FMHpDSXBKRlorODZhekZ4RTBIZlU2MVZWc25I?= =?utf-8?B?STFMcHNmcWpwSStZNUR2emRveTMxY04ybmx4OGhGSC9XMXZDYTA5c2tvaXR2?= =?utf-8?B?OHBCU0VxZHhSM2VHT1pKamFVQmExckVzamcrMU5sNmZTNW1nNlNnK01XUjRC?= =?utf-8?B?MHlEYm9DS3dKaHBNYndkai9LQzJ5MEs5SUhnMjVXYThpdXJZc012QUhzSDM3?= =?utf-8?B?cVduZmFzcGk0YTcxc28xMGgySkJBODFBdVQwSGRQM2toVWNBeTZBZWYyN3RN?= =?utf-8?B?aDJ4dzFUeksyQzVVQTJ0SzU0aFVXT28ydXlSSGp4cmx2QVJLZkZHcEl5bStz?= =?utf-8?B?U016ODYyWGMrZmxBVXltVHJ5K3F0Q0xFS1dPTVFiaTFjRkl2Wlh5OVptWktm?= =?utf-8?B?Zk5EeVBnV0E1djBwQWcyU2FRV3hUaDF0dm9hQ2lTSzE2WVc0UjF5RUJ6Njcw?= =?utf-8?B?R2V6blBKMkZBUmhZYnVxaHlDbk52UlVuY0ZiTHp3ME8yUXdPbWM3QmRydFhk?= =?utf-8?B?MThjTXpRTk5HWDFRcTNtc1RFSUFiU3VtNnVPb3pnWVBRTGxSOE0xYmtmN1B5?= =?utf-8?B?SDZacWhETFR6VzBQV1E5R1JrL2Naa2dzbzZNT2huZEZrc2ZzOVdpV3FucVpW?= =?utf-8?B?NjZtc0puZk9VMnNrKzZadFd3RHZPa3ZsZVltU2JwMExmUjJGV29LMTR3cUlH?= =?utf-8?B?b096VTBZaHJmYStLWDhHbE13UHN3UFZRYzhmcWMyNnk4SUhnMkNmRmxINStG?= =?utf-8?B?OWhxNytzUTlYQjQwdkd6bWF1SDVwUWsvdnlEem1ZenN4WGhXT0NVS1hZaE9v?= =?utf-8?B?QTl1QTVmRTF0a040NVVQRU9sRGhBbmFhQlJjbmNDTzIvRmwxeU1YUjNCdkxk?= =?utf-8?B?Vi81d3dJU0NkVm5QV3NrWVY1VVhvRHVuZ01jZGpHWGtKYUhaVXFjSEdONUZB?= =?utf-8?B?SUl4ZVBoSVRNMElnVVo5ZXJpUU9EbGhxTU5teXBWZXp2cmU4TldQOG1wV2Ry?= =?utf-8?B?VFgwNzdYZjRqazZ6OEhTUkZlbzFubk9Iazg2cjNRdXNQRW9BSGFNemRzV3Nk?= =?utf-8?B?T2RHY3ZQaTlMeGxXMDRxU0Yva3Qxc2dJL0FLQU1CS0I2cWFWRWNxb0JrVytr?= =?utf-8?B?SC9POE1oYTRCdGZCbWFTdWZ5RFNwT1JVWTNpam4yS3YvcWE5SjI3cHBjRFFv?= =?utf-8?B?aUIyRmR4M1c2MGpMZzlkT1JuTWhldEZUWjJMOUpnL1dQbkcrNTc1YllOMXh4?= =?utf-8?B?aFlidUdJQ29JaHFpVlF6ekJZOFIvZzVLOEpoZzJJY2F4UklRQjVnck52VnUx?= =?utf-8?Q?l+GjzMF5uMV/SWbcnR+Lfmq+e1zGQvB3?= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(36860700013)(1800799024)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Aug 2024 13:05:49.3200 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 98e14d46-96cb-4569-8131-08dcbacf7ccd X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF00026367.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8412 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 23.11.2 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 08/14/24. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://git.dpdk.org/dpdk-stable/log/?h=23.11-staging This queued commit can be viewed at: https://git.dpdk.org/dpdk-stable/commit/?h=23.11-staging&id=3fc9eb2f4f24243c993862e92b1390025f0e16e6 Thanks. Xueming Li --- >From 3fc9eb2f4f24243c993862e92b1390025f0e16e6 Mon Sep 17 00:00:00 2001 From: Sivaprasad Tummala Date: Tue, 26 Mar 2024 13:55:44 +0100 Subject: [PATCH] examples: fix lcore ID restriction MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Xueming Li [ upstream commit 4b978938168b219346775ff877ac31649a36cba7 ] Currently the config option allows lcore IDs up to 255, irrespective of RTE_MAX_LCORES and needs to be fixed. The patch fixes these constraints by allowing all lcore IDs up to RTE_MAX_LCORES. Fixes: af75078fece3 ("first public release") Fixes: f88e7c175a68 ("examples/l3fwd-power: add high/regular perf cores options") Fixes: 08bd1a174461 ("examples/l3fwd-graph: add graph-based l3fwd skeleton") Fixes: d299106e8e31 ("examples/ipsec-secgw: add IPsec sample application") Fixes: 0e8f47491f09 ("examples/vm_power: add command to query CPU frequency") Fixes: de3cfa2c9823 ("sched: initial import") Cc: stable@dpdk.org Signed-off-by: Sivaprasad Tummala Acked-by: Konstantin Ananyev Acked-by: Morten Brørup Acked-by: Ferruh Yigit --- examples/ipsec-secgw/event_helper.h | 2 +- examples/ipsec-secgw/ipsec-secgw.c | 21 ++++++++++++------- examples/ipsec-secgw/ipsec.c | 2 +- examples/ipsec-secgw/ipsec.h | 4 ++-- examples/l3fwd-graph/main.c | 14 ++++++------- examples/l3fwd-power/main.c | 18 +++++++++------- examples/l3fwd-power/main.h | 2 +- examples/l3fwd-power/perf_core.c | 11 +++++++--- examples/l3fwd/main.c | 20 +++++++++++------- examples/qos_sched/args.c | 6 +++--- .../guest_cli/vm_power_cli_guest.c | 4 ++-- 11 files changed, 61 insertions(+), 43 deletions(-) diff --git a/examples/ipsec-secgw/event_helper.h b/examples/ipsec-secgw/event_helper.h index dfb81bfcf1..be635685b4 100644 --- a/examples/ipsec-secgw/event_helper.h +++ b/examples/ipsec-secgw/event_helper.h @@ -102,7 +102,7 @@ struct eh_event_link_info { /**< Event port ID */ uint8_t eventq_id; /**< Event queue to be linked to the port */ - uint8_t lcore_id; + uint32_t lcore_id; /**< Lcore to be polling on this port */ }; diff --git a/examples/ipsec-secgw/ipsec-secgw.c b/examples/ipsec-secgw/ipsec-secgw.c index 782535f4b5..2d004d82fd 100644 --- a/examples/ipsec-secgw/ipsec-secgw.c +++ b/examples/ipsec-secgw/ipsec-secgw.c @@ -221,7 +221,7 @@ static const char *cfgfile; struct lcore_params { uint16_t port_id; uint16_t queue_id; - uint8_t lcore_id; + uint32_t lcore_id; } __rte_cache_aligned; static struct lcore_params lcore_params_array[MAX_LCORE_PARAMS]; @@ -807,7 +807,7 @@ check_flow_params(uint16_t fdir_portid, uint8_t fdir_qid) static int32_t check_poll_mode_params(struct eh_conf *eh_conf) { - uint8_t lcore; + uint32_t lcore; uint16_t portid; uint16_t i; int32_t socket_id; @@ -826,13 +826,13 @@ check_poll_mode_params(struct eh_conf *eh_conf) for (i = 0; i < nb_lcore_params; ++i) { lcore = lcore_params[i].lcore_id; if (!rte_lcore_is_enabled(lcore)) { - printf("error: lcore %hhu is not enabled in " + printf("error: lcore %u is not enabled in " "lcore mask\n", lcore); return -1; } socket_id = rte_lcore_to_socket_id(lcore); if (socket_id != 0 && numa_on == 0) { - printf("warning: lcore %hhu is on socket %d " + printf("warning: lcore %u is on socket %d " "with numa off\n", lcore, socket_id); } @@ -867,7 +867,7 @@ static int32_t init_lcore_rx_queues(void) { uint16_t i, nb_rx_queue; - uint8_t lcore; + uint32_t lcore; for (i = 0; i < nb_lcore_params; ++i) { lcore = lcore_params[i].lcore_id; @@ -1048,7 +1048,11 @@ parse_config(const char *q_arg) char *str_fld[_NUM_FLD]; int32_t i; uint32_t size; - uint32_t max_fld[_NUM_FLD] = {255, RTE_MAX_QUEUES_PER_PORT, 255}; + uint32_t max_fld[_NUM_FLD] = { + 255, + RTE_MAX_QUEUES_PER_PORT, + RTE_MAX_LCORE + }; nb_lcore_params = 0; @@ -1082,7 +1086,7 @@ parse_config(const char *q_arg) lcore_params_array[nb_lcore_params].queue_id = (uint16_t)int_fld[FLD_QUEUE]; lcore_params_array[nb_lcore_params].lcore_id = - (uint8_t)int_fld[FLD_LCORE]; + (uint32_t)int_fld[FLD_LCORE]; ++nb_lcore_params; } lcore_params = lcore_params_array; @@ -1918,7 +1922,8 @@ port_init(uint16_t portid, uint64_t req_rx_offloads, uint64_t req_tx_offloads, struct rte_eth_dev_info dev_info; struct rte_eth_txconf *txconf; uint16_t nb_tx_queue, nb_rx_queue; - uint16_t tx_queueid, rx_queueid, queue, lcore_id; + uint16_t tx_queueid, rx_queueid, queue; + uint32_t lcore_id; int32_t ret, socket_id; struct lcore_conf *qconf; struct rte_ether_addr ethaddr; diff --git a/examples/ipsec-secgw/ipsec.c b/examples/ipsec-secgw/ipsec.c index c321108119..b52b0ffc3d 100644 --- a/examples/ipsec-secgw/ipsec.c +++ b/examples/ipsec-secgw/ipsec.c @@ -259,7 +259,7 @@ create_lookaside_session(struct ipsec_ctx *ipsec_ctx_lcore[], continue; /* Looking for cryptodev, which can handle this SA */ - key.lcore_id = (uint8_t)lcore_id; + key.lcore_id = lcore_id; key.cipher_algo = (uint8_t)sa->cipher_algo; key.auth_algo = (uint8_t)sa->auth_algo; key.aead_algo = (uint8_t)sa->aead_algo; diff --git a/examples/ipsec-secgw/ipsec.h b/examples/ipsec-secgw/ipsec.h index 649fb36871..d4ecfdf08d 100644 --- a/examples/ipsec-secgw/ipsec.h +++ b/examples/ipsec-secgw/ipsec.h @@ -256,11 +256,11 @@ extern struct offloads tx_offloads; * (hash key calculation reads 8 bytes if this struct is size 5 bytes). */ struct cdev_key { - uint16_t lcore_id; + uint32_t lcore_id; uint8_t cipher_algo; uint8_t auth_algo; uint8_t aead_algo; - uint8_t padding[3]; /* padding to 8-byte size should be zeroed */ + uint8_t padding; /* padding to 8-byte size should be zeroed */ }; struct socket_ctx { diff --git a/examples/l3fwd-graph/main.c b/examples/l3fwd-graph/main.c index 4b018d1e78..dbc36362c3 100644 --- a/examples/l3fwd-graph/main.c +++ b/examples/l3fwd-graph/main.c @@ -111,7 +111,7 @@ static struct lcore_conf lcore_conf[RTE_MAX_LCORE]; struct lcore_params { uint16_t port_id; uint16_t queue_id; - uint8_t lcore_id; + uint32_t lcore_id; } __rte_cache_aligned; static struct lcore_params lcore_params_array[MAX_LCORE_PARAMS]; @@ -207,7 +207,7 @@ check_lcore_params(void) { uint16_t queue, i; int socketid; - uint8_t lcore; + uint32_t lcore; for (i = 0; i < nb_lcore_params; ++i) { queue = lcore_params[i].queue_id; @@ -217,7 +217,7 @@ check_lcore_params(void) } lcore = lcore_params[i].lcore_id; if (!rte_lcore_is_enabled(lcore)) { - printf("Error: lcore %hhu is not enabled in lcore mask\n", + printf("Error: lcore %u is not enabled in lcore mask\n", lcore); return -1; } @@ -228,7 +228,7 @@ check_lcore_params(void) } socketid = rte_lcore_to_socket_id(lcore); if ((socketid != 0) && (numa_on == 0)) { - printf("Warning: lcore %hhu is on socket %d with numa off\n", + printf("Warning: lcore %u is on socket %d with numa off\n", lcore, socketid); } } @@ -282,7 +282,7 @@ static int init_lcore_rx_queues(void) { uint16_t i, nb_rx_queue; - uint8_t lcore; + uint32_t lcore; for (i = 0; i < nb_lcore_params; ++i) { lcore = lcore_params[i].lcore_id; @@ -290,7 +290,7 @@ init_lcore_rx_queues(void) if (nb_rx_queue >= MAX_RX_QUEUE_PER_LCORE) { printf("Error: too many queues (%u) for lcore: %u\n", (unsigned int)nb_rx_queue + 1, - (unsigned int)lcore); + lcore); return -1; } @@ -452,7 +452,7 @@ parse_config(const char *q_arg) lcore_params_array[nb_lcore_params].queue_id = (uint16_t)int_fld[FLD_QUEUE]; lcore_params_array[nb_lcore_params].lcore_id = - (uint8_t)int_fld[FLD_LCORE]; + (uint32_t)int_fld[FLD_LCORE]; ++nb_lcore_params; } lcore_params = lcore_params_array; diff --git a/examples/l3fwd-power/main.c b/examples/l3fwd-power/main.c index 5045d13533..baf2bf64b2 100644 --- a/examples/l3fwd-power/main.c +++ b/examples/l3fwd-power/main.c @@ -1396,7 +1396,7 @@ static int check_lcore_params(void) { uint16_t queue, i; - uint8_t lcore; + uint32_t lcore; int socketid; for (i = 0; i < nb_lcore_params; ++i) { @@ -1407,13 +1407,13 @@ check_lcore_params(void) } lcore = lcore_params[i].lcore_id; if (!rte_lcore_is_enabled(lcore)) { - printf("error: lcore %hhu is not enabled in lcore " + printf("error: lcore %u is not enabled in lcore " "mask\n", lcore); return -1; } if ((socketid = rte_lcore_to_socket_id(lcore) != 0) && (numa_on == 0)) { - printf("warning: lcore %hhu is on socket %d with numa " + printf("warning: lcore %u is on socket %d with numa " "off\n", lcore, socketid); } if (app_mode == APP_MODE_TELEMETRY && lcore == rte_lcore_id()) { @@ -1465,14 +1465,14 @@ static int init_lcore_rx_queues(void) { uint16_t i, nb_rx_queue; - uint8_t lcore; + uint32_t lcore; for (i = 0; i < nb_lcore_params; ++i) { lcore = lcore_params[i].lcore_id; nb_rx_queue = lcore_conf[lcore].n_rx_queue; if (nb_rx_queue >= MAX_RX_QUEUE_PER_LCORE) { printf("error: too many queues (%u) for lcore: %u\n", - (unsigned)nb_rx_queue + 1, (unsigned)lcore); + (unsigned int)nb_rx_queue + 1, lcore); return -1; } else { lcore_conf[lcore].rx_queue_list[nb_rx_queue].port_id = @@ -1657,7 +1657,11 @@ parse_config(const char *q_arg) char *str_fld[_NUM_FLD]; int i; unsigned size; - unsigned int max_fld[_NUM_FLD] = {255, RTE_MAX_QUEUES_PER_PORT, 255}; + unsigned int max_fld[_NUM_FLD] = { + 255, + RTE_MAX_QUEUES_PER_PORT, + RTE_MAX_LCORE + }; nb_lcore_params = 0; @@ -1690,7 +1694,7 @@ parse_config(const char *q_arg) lcore_params_array[nb_lcore_params].queue_id = (uint16_t)int_fld[FLD_QUEUE]; lcore_params_array[nb_lcore_params].lcore_id = - (uint8_t)int_fld[FLD_LCORE]; + (uint32_t)int_fld[FLD_LCORE]; ++nb_lcore_params; } lcore_params = lcore_params_array; diff --git a/examples/l3fwd-power/main.h b/examples/l3fwd-power/main.h index 40b5194726..194bd82102 100644 --- a/examples/l3fwd-power/main.h +++ b/examples/l3fwd-power/main.h @@ -10,7 +10,7 @@ struct lcore_params { uint16_t port_id; uint16_t queue_id; - uint8_t lcore_id; + uint32_t lcore_id; } __rte_cache_aligned; extern struct lcore_params *lcore_params; diff --git a/examples/l3fwd-power/perf_core.c b/examples/l3fwd-power/perf_core.c index f34442b9d0..fbd7864cb9 100644 --- a/examples/l3fwd-power/perf_core.c +++ b/examples/l3fwd-power/perf_core.c @@ -24,7 +24,7 @@ struct perf_lcore_params { uint16_t port_id; uint16_t queue_id; uint8_t high_perf; - uint8_t lcore_idx; + uint32_t lcore_idx; } __rte_cache_aligned; static struct perf_lcore_params prf_lc_prms[MAX_LCORE_PARAMS]; @@ -132,7 +132,12 @@ parse_perf_config(const char *q_arg) char *str_fld[_NUM_FLD]; int i; unsigned int size; - unsigned int max_fld[_NUM_FLD] = {255, RTE_MAX_QUEUES_PER_PORT, 255, 255}; + unsigned int max_fld[_NUM_FLD] = { + 255, + RTE_MAX_QUEUES_PER_PORT, + 255, + RTE_MAX_LCORE + }; nb_prf_lc_prms = 0; @@ -169,7 +174,7 @@ parse_perf_config(const char *q_arg) prf_lc_prms[nb_prf_lc_prms].high_perf = !!(uint8_t)int_fld[FLD_LCORE_HP]; prf_lc_prms[nb_prf_lc_prms].lcore_idx = - (uint8_t)int_fld[FLD_LCORE_IDX]; + (uint32_t)int_fld[FLD_LCORE_IDX]; ++nb_prf_lc_prms; } diff --git a/examples/l3fwd/main.c b/examples/l3fwd/main.c index 039207b06c..47baf464e2 100644 --- a/examples/l3fwd/main.c +++ b/examples/l3fwd/main.c @@ -99,7 +99,7 @@ struct parm_cfg parm_config; struct lcore_params { uint16_t port_id; uint16_t queue_id; - uint8_t lcore_id; + uint32_t lcore_id; } __rte_cache_aligned; static struct lcore_params lcore_params_array[MAX_LCORE_PARAMS]; @@ -293,7 +293,7 @@ static int check_lcore_params(void) { uint16_t queue, i; - uint8_t lcore; + uint32_t lcore; int socketid; for (i = 0; i < nb_lcore_params; ++i) { @@ -304,12 +304,12 @@ check_lcore_params(void) } lcore = lcore_params[i].lcore_id; if (!rte_lcore_is_enabled(lcore)) { - printf("error: lcore %hhu is not enabled in lcore mask\n", lcore); + printf("error: lcore %u is not enabled in lcore mask\n", lcore); return -1; } if ((socketid = rte_lcore_to_socket_id(lcore) != 0) && (numa_on == 0)) { - printf("warning: lcore %hhu is on socket %d with numa off \n", + printf("warning: lcore %u is on socket %d with numa off\n", lcore, socketid); } } @@ -359,14 +359,14 @@ static int init_lcore_rx_queues(void) { uint16_t i, nb_rx_queue; - uint8_t lcore; + uint32_t lcore; for (i = 0; i < nb_lcore_params; ++i) { lcore = lcore_params[i].lcore_id; nb_rx_queue = lcore_conf[lcore].n_rx_queue; if (nb_rx_queue >= MAX_RX_QUEUE_PER_LCORE) { printf("error: too many queues (%u) for lcore: %u\n", - (unsigned)nb_rx_queue + 1, (unsigned)lcore); + (unsigned int)nb_rx_queue + 1, lcore); return -1; } else { lcore_conf[lcore].rx_queue_list[nb_rx_queue].port_id = @@ -500,7 +500,11 @@ parse_config(const char *q_arg) char *str_fld[_NUM_FLD]; int i; unsigned size; - uint16_t max_fld[_NUM_FLD] = {255, RTE_MAX_QUEUES_PER_PORT, 255}; + uint16_t max_fld[_NUM_FLD] = { + 255, + RTE_MAX_QUEUES_PER_PORT, + RTE_MAX_LCORE + }; nb_lcore_params = 0; @@ -532,7 +536,7 @@ parse_config(const char *q_arg) lcore_params_array[nb_lcore_params].queue_id = (uint16_t)int_fld[FLD_QUEUE]; lcore_params_array[nb_lcore_params].lcore_id = - (uint8_t)int_fld[FLD_LCORE]; + (uint32_t)int_fld[FLD_LCORE]; ++nb_lcore_params; } lcore_params = lcore_params_array; diff --git a/examples/qos_sched/args.c b/examples/qos_sched/args.c index 8d61d3e454..886542b3c1 100644 --- a/examples/qos_sched/args.c +++ b/examples/qos_sched/args.c @@ -184,10 +184,10 @@ app_parse_flow_conf(const char *conf_str) pconf->rx_port = vals[0]; pconf->tx_port = vals[1]; - pconf->rx_core = (uint8_t)vals[2]; - pconf->wt_core = (uint8_t)vals[3]; + pconf->rx_core = vals[2]; + pconf->wt_core = vals[3]; if (ret == 5) - pconf->tx_core = (uint8_t)vals[4]; + pconf->tx_core = vals[4]; else pconf->tx_core = pconf->wt_core; diff --git a/examples/vm_power_manager/guest_cli/vm_power_cli_guest.c b/examples/vm_power_manager/guest_cli/vm_power_cli_guest.c index 94bfbbaf78..5eddb47847 100644 --- a/examples/vm_power_manager/guest_cli/vm_power_cli_guest.c +++ b/examples/vm_power_manager/guest_cli/vm_power_cli_guest.c @@ -401,7 +401,7 @@ check_response_cmd(unsigned int lcore_id, int *result) struct cmd_set_cpu_freq_result { cmdline_fixed_string_t set_cpu_freq; - uint8_t lcore_id; + uint32_t lcore_id; cmdline_fixed_string_t cmd; }; @@ -444,7 +444,7 @@ cmdline_parse_token_string_t cmd_set_cpu_freq = set_cpu_freq, "set_cpu_freq"); cmdline_parse_token_num_t cmd_set_cpu_freq_core_num = TOKEN_NUM_INITIALIZER(struct cmd_set_cpu_freq_result, - lcore_id, RTE_UINT8); + lcore_id, RTE_UINT32); cmdline_parse_token_string_t cmd_set_cpu_freq_cmd_cmd = TOKEN_STRING_INITIALIZER(struct cmd_set_cpu_freq_result, cmd, "up#down#min#max#enable_turbo#disable_turbo"); -- 2.34.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2024-08-12 20:44:07.412427710 +0800 +++ 0157-examples-fix-lcore-ID-restriction.patch 2024-08-12 20:44:02.605069395 +0800 @@ -1 +1 @@ -From 4b978938168b219346775ff877ac31649a36cba7 Mon Sep 17 00:00:00 2001 +From 3fc9eb2f4f24243c993862e92b1390025f0e16e6 Mon Sep 17 00:00:00 2001 @@ -7,0 +8,3 @@ +Cc: Xueming Li + +[ upstream commit 4b978938168b219346775ff877ac31649a36cba7 ] @@ -55 +58 @@ -index 8292a262cd..5a7e1b220f 100644 +index 782535f4b5..2d004d82fd 100644 @@ -59 +62 @@ - struct __rte_cache_aligned lcore_params { + struct lcore_params { @@ -64 +67 @@ - }; + } __rte_cache_aligned; @@ -147 +150 @@ -index 6f45fdb166..a83fd2283b 100644 +index 649fb36871..d4ecfdf08d 100644 @@ -165 +168 @@ -index 0866822e93..4396e2bb3c 100644 +index 4b018d1e78..dbc36362c3 100644 @@ -169 +172 @@ - struct __rte_cache_aligned lcore_params { + struct lcore_params { @@ -174 +177 @@ - }; + } __rte_cache_aligned; @@ -232 +235 @@ -index 74e906cb5d..2976058425 100644 +index 5045d13533..baf2bf64b2 100644 @@ -235 +238 @@ -@@ -1397,7 +1397,7 @@ static int +@@ -1396,7 +1396,7 @@ static int @@ -244 +247 @@ -@@ -1408,13 +1408,13 @@ check_lcore_params(void) +@@ -1407,13 +1407,13 @@ check_lcore_params(void) @@ -260 +263 @@ -@@ -1466,14 +1466,14 @@ static int +@@ -1465,14 +1465,14 @@ static int @@ -277 +280 @@ -@@ -1658,7 +1658,11 @@ parse_config(const char *q_arg) +@@ -1657,7 +1657,11 @@ parse_config(const char *q_arg) @@ -290 +293 @@ -@@ -1691,7 +1695,7 @@ parse_config(const char *q_arg) +@@ -1690,7 +1694,7 @@ parse_config(const char *q_arg) @@ -300 +303 @@ -index 378f54794c..2461ab8da7 100644 +index 40b5194726..194bd82102 100644 @@ -304 +307 @@ - struct __rte_cache_aligned lcore_params { + struct lcore_params { @@ -309 +312 @@ - }; + } __rte_cache_aligned; @@ -313 +316 @@ -index 77248889c0..a0112b57ff 100644 +index f34442b9d0..fbd7864cb9 100644 @@ -316 +319 @@ -@@ -24,7 +24,7 @@ struct __rte_cache_aligned perf_lcore_params { +@@ -24,7 +24,7 @@ struct perf_lcore_params { @@ -322 +325 @@ - }; + } __rte_cache_aligned; @@ -349 +352 @@ -index f5f5f1a7fb..ba7083d4f3 100644 +index 039207b06c..47baf464e2 100644 @@ -353 +356 @@ - struct __rte_cache_aligned lcore_params { + struct lcore_params { @@ -358 +361 @@ - }; + } __rte_cache_aligned;