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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by CO1PEPF000042AA.mail.protection.outlook.com (10.167.243.39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7828.19 via Frontend Transport; Mon, 12 Aug 2024 12:58:04 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 12 Aug 2024 05:57:37 -0700 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Mon, 12 Aug 2024 05:57:36 -0700 From: Xueming Li To: Jiawen Wu CC: , dpdk stable Subject: patch 'net/txgbe: fix Tx hang on queue disable' has been queued to stable release 23.11.2 Date: Mon, 12 Aug 2024 20:49:09 +0800 Message-ID: <20240812125035.389667-73-xuemingl@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240812125035.389667-1-xuemingl@nvidia.com> References: <20240712110153.309690-23-xuemingl@nvidia.com> <20240812125035.389667-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042AA:EE_|IA1PR12MB6041:EE_ X-MS-Office365-Filtering-Correlation-Id: ea40b8ac-0134-4571-64b3-08dcbace6784 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Aug 2024 12:58:04.0495 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ea40b8ac-0134-4571-64b3-08dcbace6784 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6041 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 23.11.2 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 08/14/24. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://git.dpdk.org/dpdk-stable/log/?h=23.11-staging This queued commit can be viewed at: https://git.dpdk.org/dpdk-stable/commit/?h=23.11-staging&id=ed2250e120be7e7ba7b2d07b7da41c130dd10889 Thanks. Xueming Li --- >From ed2250e120be7e7ba7b2d07b7da41c130dd10889 Mon Sep 17 00:00:00 2001 From: Jiawen Wu Date: Tue, 18 Jun 2024 15:11:34 +0800 Subject: [PATCH] net/txgbe: fix Tx hang on queue disable Cc: Xueming Li [ upstream commit 8a31f4bbbbb73baf77297f00887f4b267feb7b8e ] The problem of Tx hang also occurs on Wangxun 10Gb NICs, when stop device under heavy traffic. Refer to commit ac6c5e9af56a ("net/ngbe: fix Tx hang on queue disable") Disable PCIe bus master to clear BME when stop hardware, and verify there are no pending requests. Move disabling Tx queue after disabling PCIe bus master to ensure that there are no packets left to cause Tx hang. Fixes: b1f596677d8e ("net/txgbe: support device start") Signed-off-by: Jiawen Wu --- drivers/net/txgbe/base/meson.build | 2 +- drivers/net/txgbe/base/txgbe_hw.c | 60 +++++++++++++++++++++++----- drivers/net/txgbe/base/txgbe_hw.h | 1 + drivers/net/txgbe/base/txgbe_osdep.h | 1 + drivers/net/txgbe/base/txgbe_regs.h | 3 ++ drivers/net/txgbe/base/txgbe_type.h | 1 + drivers/net/txgbe/txgbe_ethdev.c | 7 ++++ 7 files changed, 65 insertions(+), 10 deletions(-) diff --git a/drivers/net/txgbe/base/meson.build b/drivers/net/txgbe/base/meson.build index a81d6890fe..4cf90a394a 100644 --- a/drivers/net/txgbe/base/meson.build +++ b/drivers/net/txgbe/base/meson.build @@ -22,6 +22,6 @@ foreach flag: error_cflags endforeach base_lib = static_library('txgbe_base', sources, - dependencies: [static_rte_eal, static_rte_net], + dependencies: [static_rte_eal, static_rte_net, static_rte_bus_pci], c_args: c_args) base_objs = base_lib.extract_all_objects(recursive: true) diff --git a/drivers/net/txgbe/base/txgbe_hw.c b/drivers/net/txgbe/base/txgbe_hw.c index d19fd0065d..7094551fee 100644 --- a/drivers/net/txgbe/base/txgbe_hw.c +++ b/drivers/net/txgbe/base/txgbe_hw.c @@ -462,7 +462,7 @@ void txgbe_set_lan_id_multi_port(struct txgbe_hw *hw) **/ s32 txgbe_stop_hw(struct txgbe_hw *hw) { - u32 reg_val; + s32 status = 0; u16 i; /* @@ -484,16 +484,26 @@ s32 txgbe_stop_hw(struct txgbe_hw *hw) wr32(hw, TXGBE_ICR(0), TXGBE_ICR_MASK); wr32(hw, TXGBE_ICR(1), TXGBE_ICR_MASK); - /* Disable the transmit unit. Each queue must be disabled. */ - for (i = 0; i < hw->mac.max_tx_queues; i++) - wr32(hw, TXGBE_TXCFG(i), TXGBE_TXCFG_FLUSH); + wr32(hw, TXGBE_BMECTL, 0x3); /* Disable the receive unit by stopping each queue */ - for (i = 0; i < hw->mac.max_rx_queues; i++) { - reg_val = rd32(hw, TXGBE_RXCFG(i)); - reg_val &= ~TXGBE_RXCFG_ENA; - wr32(hw, TXGBE_RXCFG(i), reg_val); - } + for (i = 0; i < hw->mac.max_rx_queues; i++) + wr32(hw, TXGBE_RXCFG(i), 0); + + /* flush all queues disables */ + txgbe_flush(hw); + msec_delay(2); + + /* Prevent the PCI-E bus from hanging by disabling PCI-E master + * access and verify no pending requests + */ + status = txgbe_set_pcie_master(hw, false); + if (status) + return status; + + /* Disable the transmit unit. Each queue must be disabled. */ + for (i = 0; i < hw->mac.max_tx_queues; i++) + wr32(hw, TXGBE_TXCFG(i), 0); /* flush all queues disables */ txgbe_flush(hw); @@ -1174,6 +1184,38 @@ out: } } +s32 txgbe_set_pcie_master(struct txgbe_hw *hw, bool enable) +{ + struct rte_pci_device *pci_dev = (struct rte_pci_device *)hw->back; + s32 status = 0; + u32 i; + + if (rte_pci_set_bus_master(pci_dev, enable) < 0) { + DEBUGOUT("Cannot configure PCI bus master."); + return -1; + } + + if (enable) + goto out; + + /* Exit if master requests are blocked */ + if (!(rd32(hw, TXGBE_BMEPEND))) + goto out; + + /* Poll for master request bit to clear */ + for (i = 0; i < TXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) { + usec_delay(100); + if (!(rd32(hw, TXGBE_BMEPEND))) + goto out; + } + + DEBUGOUT("PCIe transaction pending bit also did not clear."); + status = TXGBE_ERR_MASTER_REQUESTS_PENDING; + +out: + return status; +} + /** * txgbe_acquire_swfw_sync - Acquire SWFW semaphore * @hw: pointer to hardware structure diff --git a/drivers/net/txgbe/base/txgbe_hw.h b/drivers/net/txgbe/base/txgbe_hw.h index 7031589f7c..4bf9da2d4c 100644 --- a/drivers/net/txgbe/base/txgbe_hw.h +++ b/drivers/net/txgbe/base/txgbe_hw.h @@ -40,6 +40,7 @@ s32 txgbe_setup_fc(struct txgbe_hw *hw); s32 txgbe_validate_mac_addr(u8 *mac_addr); s32 txgbe_acquire_swfw_sync(struct txgbe_hw *hw, u32 mask); void txgbe_release_swfw_sync(struct txgbe_hw *hw, u32 mask); +s32 txgbe_set_pcie_master(struct txgbe_hw *hw, bool enable); s32 txgbe_get_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr); s32 txgbe_set_san_mac_addr(struct txgbe_hw *hw, u8 *san_mac_addr); diff --git a/drivers/net/txgbe/base/txgbe_osdep.h b/drivers/net/txgbe/base/txgbe_osdep.h index b62c0b0824..0d9492c3cb 100644 --- a/drivers/net/txgbe/base/txgbe_osdep.h +++ b/drivers/net/txgbe/base/txgbe_osdep.h @@ -19,6 +19,7 @@ #include #include #include +#include #include "../txgbe_logs.h" diff --git a/drivers/net/txgbe/base/txgbe_regs.h b/drivers/net/txgbe/base/txgbe_regs.h index 79290a7afe..86896d11dc 100644 --- a/drivers/net/txgbe/base/txgbe_regs.h +++ b/drivers/net/txgbe/base/txgbe_regs.h @@ -1236,6 +1236,9 @@ enum txgbe_5tuple_protocol { #define TXGBE_TCPTMR 0x000170 #define TXGBE_ITRSEL 0x000180 +#define TXGBE_BMECTL 0x012020 +#define TXGBE_BMEPEND 0x000168 + /* P2V Mailbox */ #define TXGBE_MBMEM(i) (0x005000 + 0x40 * (i)) /* 0-63 */ #define TXGBE_MBCTL(i) (0x000600 + 4 * (i)) /* 0-63 */ diff --git a/drivers/net/txgbe/base/txgbe_type.h b/drivers/net/txgbe/base/txgbe_type.h index 75e839b7de..f52736cae9 100644 --- a/drivers/net/txgbe/base/txgbe_type.h +++ b/drivers/net/txgbe/base/txgbe_type.h @@ -29,6 +29,7 @@ #define TXGBE_FDIRCMD_CMD_POLL 10 #define TXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ #define TXGBE_SPI_TIMEOUT 10000 +#define TXGBE_PCI_MASTER_DISABLE_TIMEOUT 800 #define TXGBE_ALIGN 128 /* as intel did */ diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c index 33e4c2ec9b..af98762680 100644 --- a/drivers/net/txgbe/txgbe_ethdev.c +++ b/drivers/net/txgbe/txgbe_ethdev.c @@ -601,6 +601,7 @@ eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused) hw->hw_addr = (void *)pci_dev->mem_resource[0].addr; /* Vendor and Device ID need to be set before init of shared code */ + hw->back = pci_dev; hw->device_id = pci_dev->id.device_id; hw->vendor_id = pci_dev->id.vendor_id; if (pci_dev->id.subsystem_vendor_id == PCI_VENDOR_ID_WANGXUN) { @@ -1716,6 +1717,8 @@ txgbe_dev_start(struct rte_eth_dev *dev) hw->mac.get_link_status = true; hw->dev_start = true; + txgbe_set_pcie_master(hw, true); + /* workaround for GPIO intr lost when mng_veto bit is set */ if (txgbe_check_reset_blocked(hw)) txgbe_reinit_gpio_intr(hw); @@ -1979,6 +1982,8 @@ txgbe_dev_stop(struct rte_eth_dev *dev) adapter->rss_reta_updated = 0; wr32m(hw, TXGBE_LEDCTL, 0xFFFFFFFF, TXGBE_LEDCTL_SEL_MASK); + txgbe_set_pcie_master(hw, true); + hw->adapter_stopped = true; dev->data->dev_started = 0; hw->dev_start = false; @@ -2061,6 +2066,8 @@ txgbe_dev_close(struct rte_eth_dev *dev) txgbe_dev_free_queues(dev); + txgbe_set_pcie_master(hw, false); + /* reprogram the RAR[0] in case user changed it. */ txgbe_set_rar(hw, 0, hw->mac.addr, 0, true); -- 2.34.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2024-08-12 20:44:04.894827510 +0800 +++ 0072-net-txgbe-fix-Tx-hang-on-queue-disable.patch 2024-08-12 20:44:02.215069318 +0800 @@ -1 +1 @@ -From 8a31f4bbbbb73baf77297f00887f4b267feb7b8e Mon Sep 17 00:00:00 2001 +From ed2250e120be7e7ba7b2d07b7da41c130dd10889 Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Xueming Li + +[ upstream commit 8a31f4bbbbb73baf77297f00887f4b267feb7b8e ] @@ -17 +19,0 @@ -Cc: stable@dpdk.org @@ -142 +144 @@ -index 4fce355000..62d16a6abb 100644 +index b62c0b0824..0d9492c3cb 100644 @@ -180 +182 @@ -index fa68a5d2ca..121dccb5eb 100644 +index 33e4c2ec9b..af98762680 100644 @@ -191 +193 @@ -@@ -1717,6 +1718,8 @@ txgbe_dev_start(struct rte_eth_dev *dev) +@@ -1716,6 +1717,8 @@ txgbe_dev_start(struct rte_eth_dev *dev) @@ -200 +202 @@ -@@ -1980,6 +1983,8 @@ txgbe_dev_stop(struct rte_eth_dev *dev) +@@ -1979,6 +1982,8 @@ txgbe_dev_stop(struct rte_eth_dev *dev) @@ -209 +211 @@ -@@ -2062,6 +2067,8 @@ txgbe_dev_close(struct rte_eth_dev *dev) +@@ -2061,6 +2066,8 @@ txgbe_dev_close(struct rte_eth_dev *dev)