From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9388445E41 for ; Sat, 7 Dec 2024 09:02:32 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 8639840E4C; Sat, 7 Dec 2024 09:02:32 +0100 (CET) Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on2043.outbound.protection.outlook.com [40.107.96.43]) by mails.dpdk.org (Postfix) with ESMTP id 6851340281 for ; Sat, 7 Dec 2024 09:02:30 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=iniQHqAC0p0w46euxZp/h8wDGcUpbgaBqd+6gfQC4UvtYct9SxpoqfOp8rVyL23PLkmYiKvdfrEh+TlcudCgGI8es8LXecgKxblRFTE65aqgBYOtUxNpAFZ1lXNjnXjU9YlqTkq8h80hC9VWjOUbZk7E5bhAGcCyEVVbN2NdGv9EXHNjtrwwTdybyvfyiD+kj+mtybHAx0VnJJba2Bt5TuQKEJPolIocE5edLVPrHZOeJZrQ1USlr9mxlrBloXFGNYuTKXyPUzALoUgPE88Ht6YkH399tmxog61ks396pW4nuzWH4adY0Ou10iKzl1x9mzSc6FGweFtMqStcL9ycOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=3L8QYh657fghWT5rqbfEKCEtlX/ZOWFby89rp8Bsdr4=; b=UO5RMjIk/3yOstAeODOiLSJirSj7O99nAWNM/lEjgvPQcU5vULzB3q62i8IkOqRTBVBxu3dlbxONhtaNCtsyVBylrsyS+nWjzoxCcNqqLVafB9lqmVhEVw0i3WWclaQ4zCul0RgoD/A8vLZpfusIQZKZFstiUleGgD6qMSCAIBuOWg9xUCev8h59BL0hchR8ILpoRXAHs9RBrPcksm3/YOIwKMnm+2hlkx2KPh5wejySOU5G+4/14yH2+Ec/3lja6qmf+1+O0hNzBBeZaqR2sd0tB8ChTPvHUSj1R85GFlsLQbi+joahIc9wdprm/UkpzalOYJ97S0RUj/hhxZh/IQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.160) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=3L8QYh657fghWT5rqbfEKCEtlX/ZOWFby89rp8Bsdr4=; b=kN0rWkpiNL1TCMkf1WdDFparVgXuThQiuhzRNcL3LCS7LMgo08MSDbVzwe/ztv4EC5M7nKk08tG67RmgqeAio4I1/Xf5nIvEUKelV1ciIFtV/WYxYyjKn6A+xFr6z9ujNp/R0DDPXvg+jIZOt/i31jXdLlacl0MBdjmPdPC/s+46GcO2FpDrTfVdgpHxwbBTikIVQd9nj6/u8in40FlZiDoXxwYmH0MHN+n1rLwe1X1oGTR3X5JKV9I3D2u/ASjbWXQd4b7YX2nA7hcR8Sj1lUFm1V/NlLkWW0NIv6zv3M7zhmYtRHqZyMyjrS+tdiLdtrHXVJubtNE0YBVJGl9ZAA== Received: from PH7P220CA0108.NAMP220.PROD.OUTLOOK.COM (2603:10b6:510:32d::27) by MN2PR12MB4271.namprd12.prod.outlook.com (2603:10b6:208:1d7::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8230.17; Sat, 7 Dec 2024 08:02:23 +0000 Received: from CY4PEPF0000E9D8.namprd05.prod.outlook.com (2603:10b6:510:32d:cafe::ee) by PH7P220CA0108.outlook.office365.com (2603:10b6:510:32d::27) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8230.13 via Frontend Transport; Sat, 7 Dec 2024 08:02:23 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.160) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000E9D8.mail.protection.outlook.com (10.167.241.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8230.7 via Frontend Transport; Sat, 7 Dec 2024 08:02:23 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Sat, 7 Dec 2024 00:02:13 -0800 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Sat, 7 Dec 2024 00:02:11 -0800 From: Xueming Li To: Tim Martin CC: Xueming Li , Viacheslav Ovsiienko , dpdk stable Subject: patch 'net/mlx5: fix Tx tracing to use single clock source' has been queued to stable release 23.11.3 Date: Sat, 7 Dec 2024 15:59:29 +0800 Message-ID: <20241207080055.488538-12-xuemingl@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241207080055.488538-1-xuemingl@nvidia.com> References: <20241111062847.216344-122-xuemingl@nvidia.com> <20241207080055.488538-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D8:EE_|MN2PR12MB4271:EE_ X-MS-Office365-Filtering-Correlation-Id: 2dc66ec6-c705-4ea2-92a2-08dd16957b76 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?6+kEemwy8w4uoiRHlINNvxDpIf2ou/NWpbqQqlABufuptzV+Ls+KI2nt5tkX?= =?us-ascii?Q?Sf8uSORoEJLofg3I8kH31w0jqQl5XoLpcLsq1JXQo0boTfiS+5zFW1UI3TXY?= =?us-ascii?Q?Xr/Il/Nxi1cwakGd2FM0oYXWY5S3v3qGknUeeP2YgkQOBAZmy+vtHWF0rX9i?= =?us-ascii?Q?aGZfLKVG3x3ah6ip3bDSzkjVGctYHqIVufqXAubfWJTuz8UnqRGtq0lSCaBG?= =?us-ascii?Q?VqXx9kObqay2uZka26HOhFg+k4en19NzpOvHvmnP28UFHcHzfXRNLpZYcWuD?= =?us-ascii?Q?3SVqVLOqDAfxi4fX+yXj1oIqeYZ564b2XptPr2DuG94vdEeXsKENCJPWiYr+?= =?us-ascii?Q?lsdbI345hSBv0HJcxKrEPt1NS0JbIQahdaXWgRknqXGZZB6UuMhPDpbvdZW5?= =?us-ascii?Q?XfIsItnxu8+bC3ph9FSJ/Owx3iXgHrHwLUpNKsDEUbwQoovPDSpmzzpCBn8z?= =?us-ascii?Q?2Bg7qYFaMoMWSKc70x3vGsUFNTKfDPi0eJvvqBxywImjqjSSKyVuCHfdsDXp?= =?us-ascii?Q?T+/ltQXEb/ZALVgsgix/s5X7UbxwcFKpfSkmo9vD34t8H5pTrpJncwjcPoug?= =?us-ascii?Q?E5uB26DNBZVM8WVsvdZlEa90zbz6fNgWBvIvz19i81p5dnTFyTqyTJrsHwea?= =?us-ascii?Q?LwQq3rAn0oPIejzPE8Mo7DP9MXYHf8i6WK0AJMUmIWSc1F4yew/qduIDu51v?= =?us-ascii?Q?j4MzulTzBiaGUzupsdwSbOBJHUYW9HycrfIQPs7azFsgTnP20lkLSWlBgVxh?= =?us-ascii?Q?EVsd6zgZop3Z8Any+CeO6dJ2mOVcjKT4wKfcJ5rHqVGRPc/NA/gCEHrhDn8Q?= =?us-ascii?Q?NbbrUFyIZl8HhikNWBzk/16LPd4OsomM3SEi9ugeRGmh3OazNlY9q1MxWnao?= =?us-ascii?Q?cbKaAyRxu8aD5rDTlR4ATjC1HbuvH+XVXm90AxQoWfs7ZfFdQjPAkBGa1Wj7?= =?us-ascii?Q?h0BjRWR3+CxZd9kLidBXKbUL8hi6gejI4Wb3oRZzjHzMdIkGxOKZu79frQy2?= =?us-ascii?Q?/dz0L2KUxgsrS+bXlNt+NqGmsVUMbyS6waBSO1QjwtFap0TEde9KFg0Fa5Qw?= =?us-ascii?Q?99dvlG4iPwfxmX6vPuYUDgH9Q4rWJenyKpxavFwef1CNIx61XoCn1TtssQDF?= =?us-ascii?Q?IsZU2JBGRjbOQLq/FrzwEfElnEiONuk8ntMnCO5LN2cs1aqm1mcEBTTBfIrs?= =?us-ascii?Q?+GUDNO4aNvG+4x5TMyJqx1QRxGS+Lw2zoAMQCSrWgxEDUBejOkP8W6x4rZCK?= =?us-ascii?Q?7L3R0hLjBoWbvovGkLUoLfoEqMFBjTzuXK/pSdeDSL4IMe3inajkotMxSCMv?= =?us-ascii?Q?SgaM6D2YYzwLH2Btcg+u5J5lEAx0SerA+dijdHGBoyv8J4rUOoqRkHRXheDX?= =?us-ascii?Q?R2wHVWboLNQw4d9eUxZFHjO/kWlKXkjbux0Sq9JjFb8KOf8Pn+9+Z5BabKKD?= =?us-ascii?Q?30VB4txjOvWTPe6giuqjeLrlxisj7zC5?= X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Dec 2024 08:02:23.3159 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2dc66ec6-c705-4ea2-92a2-08dd16957b76 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D8.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4271 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 23.11.3 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 12/10/24. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://git.dpdk.org/dpdk-stable/log/?h=23.11-staging This queued commit can be viewed at: https://git.dpdk.org/dpdk-stable/commit/?h=23.11-staging&id=53b225e96b9cd6c6d952ada69ca9553b3c7d9f2d Thanks. Xueming Li --- >From 53b225e96b9cd6c6d952ada69ca9553b3c7d9f2d Mon Sep 17 00:00:00 2001 From: Tim Martin Date: Mon, 14 Oct 2024 11:04:33 +0300 Subject: [PATCH] net/mlx5: fix Tx tracing to use single clock source Cc: Xueming Li [ upstream commit 02932480ae82d7ed3c207f02cc40b508cdda6ded ] A prior commit introduced tracing for mlx5, but there is a mixture of two unrelated clocks used: the TSC for host work submission timestamps and the NIC HW clock for CQE completion times. It is necessary to have timestamps from a single common clock, and the NIC HW clock is the better choice since it can be used with externally synchronized clocks. This patch adds the NIC HW clock as an additional logged parameter for trace_tx_entry, trace_tx_exit, and trace_tx_wqe. The included trace analysis python script is also updated to use the new clock when it is available. Fixes: a1e910f5b8d4 ("net/mlx5: introduce tracepoints") Fixes: 9725191a7e14 ("net/mlx5: add Tx datapath trace analyzing script") Signed-off-by: Tim Martin Acked-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_trace.h | 9 ++++++--- drivers/net/mlx5/mlx5_tx.h | 21 +++++++++++++++++---- drivers/net/mlx5/tools/mlx5_trace.py | 12 +++++++++--- 3 files changed, 32 insertions(+), 10 deletions(-) diff --git a/drivers/net/mlx5/mlx5_trace.h b/drivers/net/mlx5/mlx5_trace.h index 888d96f60b..656dbb1a4f 100644 --- a/drivers/net/mlx5/mlx5_trace.h +++ b/drivers/net/mlx5/mlx5_trace.h @@ -22,21 +22,24 @@ extern "C" { /* TX burst subroutines trace points. */ RTE_TRACE_POINT_FP( rte_pmd_mlx5_trace_tx_entry, - RTE_TRACE_POINT_ARGS(uint16_t port_id, uint16_t queue_id), + RTE_TRACE_POINT_ARGS(uint64_t real_time, uint16_t port_id, uint16_t queue_id), + rte_trace_point_emit_u64(real_time); rte_trace_point_emit_u16(port_id); rte_trace_point_emit_u16(queue_id); ) RTE_TRACE_POINT_FP( rte_pmd_mlx5_trace_tx_exit, - RTE_TRACE_POINT_ARGS(uint16_t nb_sent, uint16_t nb_req), + RTE_TRACE_POINT_ARGS(uint64_t real_time, uint16_t nb_sent, uint16_t nb_req), + rte_trace_point_emit_u64(real_time); rte_trace_point_emit_u16(nb_sent); rte_trace_point_emit_u16(nb_req); ) RTE_TRACE_POINT_FP( rte_pmd_mlx5_trace_tx_wqe, - RTE_TRACE_POINT_ARGS(uint32_t opcode), + RTE_TRACE_POINT_ARGS(uint64_t real_time, uint32_t opcode), + rte_trace_point_emit_u64(real_time); rte_trace_point_emit_u32(opcode); ) diff --git a/drivers/net/mlx5/mlx5_tx.h b/drivers/net/mlx5/mlx5_tx.h index 42fc7ba3b3..46559426fe 100644 --- a/drivers/net/mlx5/mlx5_tx.h +++ b/drivers/net/mlx5/mlx5_tx.h @@ -401,6 +401,14 @@ static __rte_always_inline uint64_t mlx5_read_pcibar_clock(struct rte_eth_dev *d return 0; } +static __rte_always_inline uint64_t mlx5_read_pcibar_clock_from_txq(struct mlx5_txq_data *txq) +{ + struct mlx5_txq_ctrl *txq_ctrl = container_of(txq, struct mlx5_txq_ctrl, txq); + struct rte_eth_dev *dev = ETH_DEV(txq_ctrl->priv); + + return mlx5_read_pcibar_clock(dev); +} + /** * Set Software Parser flags and offsets in Ethernet Segment of WQE. * Flags must be preliminary initialized to zero. @@ -838,6 +846,7 @@ mlx5_tx_cseg_init(struct mlx5_txq_data *__rte_restrict txq, unsigned int olx) { struct mlx5_wqe_cseg *__rte_restrict cs = &wqe->cseg; + uint64_t real_time; /* For legacy MPW replace the EMPW by TSO with modifier. */ if (MLX5_TXOFF_CONFIG(MPW) && opcode == MLX5_OPCODE_ENHANCED_MPSW) @@ -851,9 +860,12 @@ mlx5_tx_cseg_init(struct mlx5_txq_data *__rte_restrict txq, cs->flags = RTE_BE32(MLX5_COMP_ONLY_FIRST_ERR << MLX5_COMP_MODE_OFFSET); cs->misc = RTE_BE32(0); - if (__rte_trace_point_fp_is_enabled()) - rte_pmd_mlx5_trace_tx_entry(txq->port_id, txq->idx); - rte_pmd_mlx5_trace_tx_wqe((txq->wqe_ci << 8) | opcode); + if (__rte_trace_point_fp_is_enabled()) { + real_time = mlx5_read_pcibar_clock_from_txq(txq); + if (!loc->pkts_sent) + rte_pmd_mlx5_trace_tx_entry(real_time, txq->port_id, txq->idx); + rte_pmd_mlx5_trace_tx_wqe(real_time, (txq->wqe_ci << 8) | opcode); + } } /** @@ -3815,7 +3827,8 @@ burst_exit: __mlx5_tx_free_mbuf(txq, pkts, loc.mbuf_free, olx); /* Trace productive bursts only. */ if (__rte_trace_point_fp_is_enabled() && loc.pkts_sent) - rte_pmd_mlx5_trace_tx_exit(loc.pkts_sent, pkts_n); + rte_pmd_mlx5_trace_tx_exit(mlx5_read_pcibar_clock_from_txq(txq), + loc.pkts_sent, pkts_n); return loc.pkts_sent; } diff --git a/drivers/net/mlx5/tools/mlx5_trace.py b/drivers/net/mlx5/tools/mlx5_trace.py index 67461520a9..5eb634a490 100755 --- a/drivers/net/mlx5/tools/mlx5_trace.py +++ b/drivers/net/mlx5/tools/mlx5_trace.py @@ -174,7 +174,9 @@ def do_tx_entry(msg, trace): return # allocate the new burst and append to the queue burst = MlxBurst() - burst.call_ts = msg.default_clock_snapshot.ns_from_origin + burst.call_ts = event["real_time"] + if burst.call_ts == 0: + burst.call_ts = msg.default_clock_snapshot.ns_from_origin trace.tx_blst[cpu_id] = burst pq_id = event["port_id"] << 16 | event["queue_id"] queue = trace.tx_qlst.get(pq_id) @@ -194,7 +196,9 @@ def do_tx_exit(msg, trace): burst = trace.tx_blst.get(cpu_id) if burst is None: return - burst.done_ts = msg.default_clock_snapshot.ns_from_origin + burst.done_ts = event["real_time"] + if burst.done_ts == 0: + burst.done_ts = msg.default_clock_snapshot.ns_from_origin burst.req = event["nb_req"] burst.done = event["nb_sent"] trace.tx_blst.pop(cpu_id) @@ -210,7 +214,9 @@ def do_tx_wqe(msg, trace): wqe = MlxWqe() wqe.wait_ts = trace.tx_wlst.get(cpu_id) if wqe.wait_ts is None: - wqe.wait_ts = msg.default_clock_snapshot.ns_from_origin + wqe.wait_ts = event["real_time"] + if wqe.wait_ts == 0: + wqe.wait_ts = msg.default_clock_snapshot.ns_from_origin wqe.opcode = event["opcode"] burst.wqes.append(wqe) -- 2.34.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2024-12-06 23:26:44.517307221 +0800 +++ 0011-net-mlx5-fix-Tx-tracing-to-use-single-clock-source.patch 2024-12-06 23:26:43.863044829 +0800 @@ -1 +1 @@ -From 02932480ae82d7ed3c207f02cc40b508cdda6ded Mon Sep 17 00:00:00 2001 +From 53b225e96b9cd6c6d952ada69ca9553b3c7d9f2d Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Xueming Li + +[ upstream commit 02932480ae82d7ed3c207f02cc40b508cdda6ded ] @@ -19 +21,0 @@ -Cc: stable@dpdk.org @@ -30 +32 @@ -index a8f0b372c8..4fc3584acc 100644 +index 888d96f60b..656dbb1a4f 100644 @@ -62 +64 @@ -index 587e6a9f7d..55568c41b1 100644 +index 42fc7ba3b3..46559426fe 100644 @@ -65 +67 @@ -@@ -404,6 +404,14 @@ static __rte_always_inline uint64_t mlx5_read_pcibar_clock(struct rte_eth_dev *d +@@ -401,6 +401,14 @@ static __rte_always_inline uint64_t mlx5_read_pcibar_clock(struct rte_eth_dev *d @@ -80 +82 @@ -@@ -841,6 +849,7 @@ mlx5_tx_cseg_init(struct mlx5_txq_data *__rte_restrict txq, +@@ -838,6 +846,7 @@ mlx5_tx_cseg_init(struct mlx5_txq_data *__rte_restrict txq, @@ -88 +90 @@ -@@ -854,9 +863,12 @@ mlx5_tx_cseg_init(struct mlx5_txq_data *__rte_restrict txq, +@@ -851,9 +860,12 @@ mlx5_tx_cseg_init(struct mlx5_txq_data *__rte_restrict txq, @@ -104 +106 @@ -@@ -3818,7 +3830,8 @@ burst_exit: +@@ -3815,7 +3827,8 @@ burst_exit: