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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by CY4PEPF0000E9D5.mail.protection.outlook.com (10.167.241.68) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8230.7 via Frontend Transport; Sat, 7 Dec 2024 08:02:57 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Sat, 7 Dec 2024 00:02:47 -0800 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Sat, 7 Dec 2024 00:02:45 -0800 From: Xueming Li To: Igor Gutorov CC: Xueming Li , Viacheslav Ovsiienko , dpdk stable Subject: patch 'net/mlx5: fix reported Rx/Tx descriptor limits' has been queued to stable release 23.11.3 Date: Sat, 7 Dec 2024 15:59:37 +0800 Message-ID: <20241207080055.488538-20-xuemingl@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241207080055.488538-1-xuemingl@nvidia.com> References: <20241111062847.216344-122-xuemingl@nvidia.com> <20241207080055.488538-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D5:EE_|DS7PR12MB5935:EE_ X-MS-Office365-Filtering-Correlation-Id: 6f74ac12-0f24-44d4-9c19-08dd16958fdb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026)(7053199007); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Dec 2024 08:02:57.5325 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6f74ac12-0f24-44d4-9c19-08dd16958fdb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D5.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5935 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 23.11.3 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 12/10/24. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://git.dpdk.org/dpdk-stable/log/?h=23.11-staging This queued commit can be viewed at: https://git.dpdk.org/dpdk-stable/commit/?h=23.11-staging&id=10f46d35b3254f4a43c268b873ab571fde3c6722 Thanks. Xueming Li --- >From 10f46d35b3254f4a43c268b873ab571fde3c6722 Mon Sep 17 00:00:00 2001 From: Igor Gutorov Date: Wed, 7 Aug 2024 23:44:05 +0300 Subject: [PATCH] net/mlx5: fix reported Rx/Tx descriptor limits Cc: Xueming Li [ upstream commit 4c3d7961d9002bb715a8ee76bcf464d633316d4c ] Currently, `rte_eth_dev_info.rx_desc_lim.nb_max` as well as `rte_eth_dev_info.tx_desc_lim.nb_max` shows 65535 as the limit, which results in a few problems: * It is not the actual Rx/Tx queue limit * Allocating an Rx queue and passing `rx_desc_lim.nb_max` results in an integer overflow and 0 ring size: ``` rte_eth_rx_queue_setup(0, 0, rx_desc_lim.nb_max, 0, NULL, mb_pool); ``` Which overflows ring size and generates the following log: ``` mlx5_net: port 0 increased number of descriptors in Rx queue 0 to the next power of two (0) ``` The same holds for allocating a Tx queue. Fixes: e60fbd5b24fc ("mlx5: add device configure/start/stop") Signed-off-by: Igor Gutorov Acked-by: Viacheslav Ovsiienko --- drivers/common/mlx5/mlx5_devx_cmds.c | 1 + drivers/common/mlx5/mlx5_devx_cmds.h | 1 + drivers/net/mlx5/mlx5_ethdev.c | 4 ++++ drivers/net/mlx5/mlx5_rxq.c | 8 ++++++++ drivers/net/mlx5/mlx5_txq.c | 8 ++++++++ 5 files changed, 22 insertions(+) diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c index 630ab96a8f..9e2d7ce86f 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.c +++ b/drivers/common/mlx5/mlx5_devx_cmds.c @@ -1019,6 +1019,7 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, attr->log_max_qp = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp); attr->log_max_cq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_cq_sz); attr->log_max_qp_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_qp_sz); + attr->log_max_wq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_wq_sz); attr->log_max_mrw_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_mrw_sz); attr->log_max_pd = MLX5_GET(cmd_hca_cap, hcattr, log_max_pd); attr->log_max_srq = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq); diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h index b814c8becc..028cf2abb9 100644 --- a/drivers/common/mlx5/mlx5_devx_cmds.h +++ b/drivers/common/mlx5/mlx5_devx_cmds.h @@ -264,6 +264,7 @@ struct mlx5_hca_attr { struct mlx5_hca_flow_attr flow; struct mlx5_hca_flex_attr flex; struct mlx5_hca_crypto_mmo_attr crypto_mmo; + uint8_t log_max_wq_sz; int log_max_qp_sz; int log_max_cq_sz; int log_max_qp; diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c index ec4bdd8af1..8f29e58cda 100644 --- a/drivers/net/mlx5/mlx5_ethdev.c +++ b/drivers/net/mlx5/mlx5_ethdev.c @@ -351,6 +351,10 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) info->flow_type_rss_offloads = ~MLX5_RSS_HF_MASK; mlx5_set_default_params(dev, info); mlx5_set_txlimit_params(dev, info); + info->rx_desc_lim.nb_max = + 1 << priv->sh->cdev->config.hca_attr.log_max_wq_sz; + info->tx_desc_lim.nb_max = + 1 << priv->sh->cdev->config.hca_attr.log_max_wq_sz; if (priv->sh->cdev->config.hca_attr.mem_rq_rmp && priv->obj_ops.rxq_obj_new == devx_obj_ops.rxq_obj_new) info->dev_capa |= RTE_ETH_DEV_CAPA_RXQ_SHARE; diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index e45cca9133..82d8f29b31 100644 --- a/drivers/net/mlx5/mlx5_rxq.c +++ b/drivers/net/mlx5/mlx5_rxq.c @@ -655,6 +655,14 @@ mlx5_rx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t *desc, struct mlx5_rxq_priv *rxq; bool empty; + if (*desc > 1 << priv->sh->cdev->config.hca_attr.log_max_wq_sz) { + DRV_LOG(ERR, + "port %u number of descriptors requested for Rx queue" + " %u is more than supported", + dev->data->port_id, idx); + rte_errno = EINVAL; + return -EINVAL; + } if (!rte_is_power_of_2(*desc)) { *desc = 1 << log2above(*desc); DRV_LOG(WARNING, diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c index aac078a6ed..52a39ae073 100644 --- a/drivers/net/mlx5/mlx5_txq.c +++ b/drivers/net/mlx5/mlx5_txq.c @@ -332,6 +332,14 @@ mlx5_tx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t *desc) { struct mlx5_priv *priv = dev->data->dev_private; + if (*desc > 1 << priv->sh->cdev->config.hca_attr.log_max_wq_sz) { + DRV_LOG(ERR, + "port %u number of descriptors requested for Tx queue" + " %u is more than supported", + dev->data->port_id, idx); + rte_errno = EINVAL; + return -EINVAL; + } if (*desc <= MLX5_TX_COMP_THRESH) { DRV_LOG(WARNING, "port %u number of descriptors requested for Tx queue" -- 2.34.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2024-12-06 23:26:44.788275618 +0800 +++ 0019-net-mlx5-fix-reported-Rx-Tx-descriptor-limits.patch 2024-12-06 23:26:43.893044828 +0800 @@ -1 +1 @@ -From 4c3d7961d9002bb715a8ee76bcf464d633316d4c Mon Sep 17 00:00:00 2001 +From 10f46d35b3254f4a43c268b873ab571fde3c6722 Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Xueming Li + +[ upstream commit 4c3d7961d9002bb715a8ee76bcf464d633316d4c ] @@ -26 +28,0 @@ -Cc: stable@dpdk.org @@ -39 +41 @@ -index 9710dcedd3..a75f011750 100644 +index 630ab96a8f..9e2d7ce86f 100644 @@ -42 +44 @@ -@@ -1027,6 +1027,7 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, +@@ -1019,6 +1019,7 @@ mlx5_devx_cmd_query_hca_attr(void *ctx, @@ -51 +53 @@ -index 6cf7999c46..2ad9e5414f 100644 +index b814c8becc..028cf2abb9 100644 @@ -54 +56 @@ -@@ -267,6 +267,7 @@ struct mlx5_hca_attr { +@@ -264,6 +264,7 @@ struct mlx5_hca_attr { @@ -63 +65 @@ -index 6f24d649e0..7708a0b808 100644 +index ec4bdd8af1..8f29e58cda 100644 @@ -66 +68 @@ -@@ -359,6 +359,10 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) +@@ -351,6 +351,10 @@ mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info) @@ -78 +80 @@ -index c6655b7db4..5eac224b76 100644 +index e45cca9133..82d8f29b31 100644 @@ -97 +99 @@ -index f05534e168..3e93517323 100644 +index aac078a6ed..52a39ae073 100644 @@ -100 +102 @@ -@@ -333,6 +333,14 @@ mlx5_tx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t *desc) +@@ -332,6 +332,14 @@ mlx5_tx_queue_pre_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t *desc)