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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BL02EPF00021F69.mail.protection.outlook.com (10.167.249.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8230.7 via Frontend Transport; Sat, 7 Dec 2024 08:08:03 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Sat, 7 Dec 2024 00:07:54 -0800 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Sat, 7 Dec 2024 00:07:52 -0800 From: Xueming Li To: Bing Zhao CC: Xueming Li , Viacheslav Ovsiienko , Dariusz Sosnowski , "dpdk stable" Subject: patch 'net/mlx5: fix Rx queue control management' has been queued to stable release 23.11.3 Date: Sat, 7 Dec 2024 16:00:29 +0800 Message-ID: <20241207080055.488538-72-xuemingl@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241207080055.488538-1-xuemingl@nvidia.com> References: <20241111062847.216344-122-xuemingl@nvidia.com> <20241207080055.488538-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F69:EE_|PH7PR12MB7017:EE_ X-MS-Office365-Filtering-Correlation-Id: 7a3a24e4-bd69-4f5d-14d4-08dd1696466d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Dec 2024 08:08:03.6750 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7a3a24e4-bd69-4f5d-14d4-08dd1696466d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F69.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7017 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 23.11.3 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 12/10/24. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://git.dpdk.org/dpdk-stable/log/?h=23.11-staging This queued commit can be viewed at: https://git.dpdk.org/dpdk-stable/commit/?h=23.11-staging&id=0c7dbcd34ae74fdc5a51525690f5ba70ad6edc25 Thanks. Xueming Li --- >From 0c7dbcd34ae74fdc5a51525690f5ba70ad6edc25 Mon Sep 17 00:00:00 2001 From: Bing Zhao Date: Mon, 4 Nov 2024 18:15:41 +0200 Subject: [PATCH] net/mlx5: fix Rx queue control management Cc: Xueming Li [ upstream commit 3c9a82fa6edc06c1d4dc6c0ac53609002c4d9462 ] With the shared Rx queue feature introduced, the control and private Rx queue structures are decoupled, each control structure can be shared for multiple queue for all representors inside a domain. So it should be only managed by the shared context instead of any private data of each device. The previous workaround is using a flag to check the owner (allocator) of the structure and handle it only on that device closing stage. A proper formal solution is to add a reference count for each control structure and only free the structure when there is no reference to it to get rid of the UAF issue. Fixes: f957ac996435 ("net/mlx5: workaround list management of Rx queue control") Fixes: bcc220cb57d7 ("net/mlx5: fix shared Rx queue list management") Signed-off-by: Bing Zhao Acked-by: Viacheslav Ovsiienko Acked-by: Dariusz Sosnowski --- drivers/net/mlx5/mlx5.h | 1 - drivers/net/mlx5/mlx5_flow.c | 4 ++-- drivers/net/mlx5/mlx5_rx.h | 3 +-- drivers/net/mlx5/mlx5_rxq.c | 20 ++++++++++---------- 4 files changed, 13 insertions(+), 15 deletions(-) diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h index bce1d9e749..9a6bd976c2 100644 --- a/drivers/net/mlx5/mlx5.h +++ b/drivers/net/mlx5/mlx5.h @@ -1886,7 +1886,6 @@ struct mlx5_priv { uint32_t ctrl_flows; /* Control flow rules. */ rte_spinlock_t flow_list_lock; struct mlx5_obj_ops obj_ops; /* HW objects operations. */ - LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */ LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */ struct mlx5_list *hrxqs; /* Hash Rx queues. */ LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */ diff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c index fdc7c3ea54..6286eef010 100644 --- a/drivers/net/mlx5/mlx5_flow.c +++ b/drivers/net/mlx5/mlx5_flow.c @@ -1748,13 +1748,13 @@ flow_rxq_mark_flag_set(struct rte_eth_dev *dev) opriv->domain_id != priv->domain_id || opriv->mark_enabled) continue; - LIST_FOREACH(rxq_ctrl, &opriv->rxqsctrl, next) { + LIST_FOREACH(rxq_ctrl, &opriv->sh->shared_rxqs, share_entry) { rxq_ctrl->rxq.mark = 1; } opriv->mark_enabled = 1; } } else { - LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) { + LIST_FOREACH(rxq_ctrl, &priv->sh->shared_rxqs, share_entry) { rxq_ctrl->rxq.mark = 1; } priv->mark_enabled = 1; diff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h index 08ab0a042d..f78fae26d3 100644 --- a/drivers/net/mlx5/mlx5_rx.h +++ b/drivers/net/mlx5/mlx5_rx.h @@ -151,13 +151,13 @@ struct mlx5_rxq_data { /* RX queue control descriptor. */ struct mlx5_rxq_ctrl { struct mlx5_rxq_data rxq; /* Data path structure. */ - LIST_ENTRY(mlx5_rxq_ctrl) next; /* Pointer to the next element. */ LIST_HEAD(priv, mlx5_rxq_priv) owners; /* Owner rxq list. */ struct mlx5_rxq_obj *obj; /* Verbs/DevX elements. */ struct mlx5_dev_ctx_shared *sh; /* Shared context. */ bool is_hairpin; /* Whether RxQ type is Hairpin. */ unsigned int socket; /* CPU socket ID for allocations. */ LIST_ENTRY(mlx5_rxq_ctrl) share_entry; /* Entry in shared RXQ list. */ + RTE_ATOMIC(uint32_t) ctrl_ref; /* Reference counter. */ uint32_t share_group; /* Group ID of shared RXQ. */ uint16_t share_qid; /* Shared RxQ ID in group. */ unsigned int started:1; /* Whether (shared) RXQ has been started. */ @@ -173,7 +173,6 @@ struct mlx5_rxq_ctrl { /* RX queue private data. */ struct mlx5_rxq_priv { uint16_t idx; /* Queue index. */ - bool possessor; /* Shared rxq_ctrl allocated for the 1st time. */ uint32_t refcnt; /* Reference counter. */ struct mlx5_rxq_ctrl *ctrl; /* Shared Rx Queue. */ LIST_ENTRY(mlx5_rxq_priv) owner_entry; /* Entry in shared rxq_ctrl. */ diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index 82d8f29b31..aa2e8fd9e3 100644 --- a/drivers/net/mlx5/mlx5_rxq.c +++ b/drivers/net/mlx5/mlx5_rxq.c @@ -946,7 +946,6 @@ mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, rte_errno = ENOMEM; return -rte_errno; } - rxq->possessor = true; } rxq->priv = priv; rxq->idx = idx; @@ -954,6 +953,7 @@ mlx5_rx_queue_setup(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, /* Join owner list. */ LIST_INSERT_HEAD(&rxq_ctrl->owners, rxq, owner_entry); rxq->ctrl = rxq_ctrl; + rte_atomic_fetch_add_explicit(&rxq_ctrl->ctrl_ref, 1, rte_memory_order_relaxed); mlx5_rxq_ref(dev, idx); DRV_LOG(DEBUG, "port %u adding Rx queue %u to list", dev->data->port_id, idx); @@ -1971,9 +1971,9 @@ mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, tmpl->rxq.shared = 1; tmpl->share_group = conf->share_group; tmpl->share_qid = conf->share_qid; - LIST_INSERT_HEAD(&priv->sh->shared_rxqs, tmpl, share_entry); } - LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next); + LIST_INSERT_HEAD(&priv->sh->shared_rxqs, tmpl, share_entry); + rte_atomic_store_explicit(&tmpl->ctrl_ref, 1, rte_memory_order_relaxed); return tmpl; error: mlx5_mr_btree_free(&tmpl->rxq.mr_ctrl.cache_bh); @@ -2025,9 +2025,9 @@ mlx5_rxq_hairpin_new(struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq, tmpl->rxq.mr_ctrl.cache_bh = (struct mlx5_mr_btree) { 0 }; tmpl->rxq.idx = idx; rxq->hairpin_conf = *hairpin_conf; - rxq->possessor = true; mlx5_rxq_ref(dev, idx); - LIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next); + LIST_INSERT_HEAD(&priv->sh->shared_rxqs, tmpl, share_entry); + rte_atomic_store_explicit(&tmpl->ctrl_ref, 1, rte_memory_order_relaxed); return tmpl; } @@ -2293,16 +2293,16 @@ mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx) RTE_ETH_QUEUE_STATE_STOPPED; } } else { /* Refcnt zero, closing device. */ - if (rxq->possessor) - LIST_REMOVE(rxq_ctrl, next); LIST_REMOVE(rxq, owner_entry); if (LIST_EMPTY(&rxq_ctrl->owners)) { if (!rxq_ctrl->is_hairpin) mlx5_mr_btree_free (&rxq_ctrl->rxq.mr_ctrl.cache_bh); - if (rxq_ctrl->rxq.shared) + if (rte_atomic_fetch_sub_explicit(&rxq_ctrl->ctrl_ref, 1, + rte_memory_order_relaxed) == 1) { LIST_REMOVE(rxq_ctrl, share_entry); - mlx5_free(rxq_ctrl); + mlx5_free(rxq_ctrl); + } } dev->data->rx_queues[idx] = NULL; mlx5_free(rxq); @@ -2327,7 +2327,7 @@ mlx5_rxq_verify(struct rte_eth_dev *dev) struct mlx5_rxq_ctrl *rxq_ctrl; int ret = 0; - LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) { + LIST_FOREACH(rxq_ctrl, &priv->sh->shared_rxqs, share_entry) { DRV_LOG(DEBUG, "port %u Rx Queue %u still referenced", dev->data->port_id, rxq_ctrl->rxq.idx); ++ret; -- 2.34.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2024-12-06 23:26:46.451298100 +0800 +++ 0071-net-mlx5-fix-Rx-queue-control-management.patch 2024-12-06 23:26:44.043044827 +0800 @@ -1 +1 @@ -From 3c9a82fa6edc06c1d4dc6c0ac53609002c4d9462 Mon Sep 17 00:00:00 2001 +From 0c7dbcd34ae74fdc5a51525690f5ba70ad6edc25 Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Xueming Li + +[ upstream commit 3c9a82fa6edc06c1d4dc6c0ac53609002c4d9462 ] @@ -21 +23,0 @@ -CC: stable@dpdk.org @@ -34 +36 @@ -index bc25d72c0e..6e8295110e 100644 +index bce1d9e749..9a6bd976c2 100644 @@ -37 +39 @@ -@@ -2004,7 +2004,6 @@ struct mlx5_priv { +@@ -1886,7 +1886,6 @@ struct mlx5_priv { @@ -46 +48 @@ -index f8cfa661ec..d631ed150c 100644 +index fdc7c3ea54..6286eef010 100644 @@ -49 +51 @@ -@@ -1648,13 +1648,13 @@ flow_rxq_mark_flag_set(struct rte_eth_dev *dev) +@@ -1748,13 +1748,13 @@ flow_rxq_mark_flag_set(struct rte_eth_dev *dev) @@ -66 +68 @@ -index 9bcb43b007..da7c448948 100644 +index 08ab0a042d..f78fae26d3 100644 @@ -69 +71 @@ -@@ -151,13 +151,13 @@ struct __rte_cache_aligned mlx5_rxq_data { +@@ -151,13 +151,13 @@ struct mlx5_rxq_data { @@ -89 +91 @@ - RTE_ATOMIC(uint32_t) refcnt; /* Reference counter. */ + uint32_t refcnt; /* Reference counter. */ @@ -93 +95 @@ -index 5eac224b76..d437835b73 100644 +index 82d8f29b31..aa2e8fd9e3 100644 @@ -112 +114 @@ -@@ -1970,9 +1970,9 @@ mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, +@@ -1971,9 +1971,9 @@ mlx5_rxq_new(struct rte_eth_dev *dev, uint16_t idx, uint16_t desc, @@ -124 +126 @@ -@@ -2024,9 +2024,9 @@ mlx5_rxq_hairpin_new(struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq, +@@ -2025,9 +2025,9 @@ mlx5_rxq_hairpin_new(struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq, @@ -136 +138 @@ -@@ -2292,16 +2292,16 @@ mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx) +@@ -2293,16 +2293,16 @@ mlx5_rxq_release(struct rte_eth_dev *dev, uint16_t idx) @@ -157 +159 @@ -@@ -2326,7 +2326,7 @@ mlx5_rxq_verify(struct rte_eth_dev *dev) +@@ -2327,7 +2327,7 @@ mlx5_rxq_verify(struct rte_eth_dev *dev)