patch 'common/mlx5: fix misalignment' has been queued to stable release 23.11.3

[Xueming Li <xuemingl@nvidia.com>]

Hi,

FYI, your patch has been queued to stable release 23.11.3

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 12/10/24. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://git.dpdk.org/dpdk-stable/log/?h=23.11-staging

This queued commit can be viewed at:
https://git.dpdk.org/dpdk-stable/commit/?h=23.11-staging&id=83af285731ae630e8db81a4d5a3d2e93f6826726

Thanks.

Xueming Li <xuemingl@nvidia.com>

---
From 83af285731ae630e8db81a4d5a3d2e93f6826726 Mon Sep 17 00:00:00 2001
From: Shani Peretz <shperetz@nvidia.com>
Date: Tue, 12 Nov 2024 10:21:26 +0200
Subject: [PATCH] common/mlx5: fix misalignment
Cc: Xueming Li <xuemingl@nvidia.com>

[ upstream commit 90967539d0d1afcfd5237ed85efdc430359a0e6b ]

ASan reported a runtime error due to misalignment
involving three structures.

The first issue arises when accessing
l_inconst->cache[MLX5_LIST_GLOBAL]->h.
If struct mlx5_list_cache is not properly aligned, the pointer gc,
assigned to l_inconst->cache[MLX5_LIST_GLOBAL], could be misaligned.
To address this, the __rte_aligned(16) attribute was added to
struct mlx5_list_inconst in struct mlx5_list, which includes struct
mlx5_list_cache, ensuring that the entire mlx5_list structure,
including mlx5_list_cache, is aligned to 64 bytes.

To resolve misalignment issues with struct mlx5_flow_handle,
The initialization of resources for the ipool ensures that
the ipool size is rounded up to the 8-byte boundary

The error in assigning values to actions[i] was due to potential
padding or misalignment in struct mlx5_modification_cmd.
To prevent such issues, the __rte_packed attribute was added to
struct mlx5_modification_cmd, ensuring that the structure is packed
without extra padding which helps avoid misaligned memory accesses.

Two performance degradation tests were conducted.
Following are the results comparing this commit to the most recent
commit in mlnx_dpdk_22.11 at that time (b69408ae453).

Before asan misalignment fix (average kflows/sec) -
Insertion - 4461.269, Deletion - 7799.9992
After:
Insertion - 4579.0642 , Deletion - 7913.0034

Fixes: 9a4c36880704 ("common/mlx5: optimize cache list object memory")

Signed-off-by: Shani Peretz <shperetz@nvidia.com>
Acked-by: Bing Zhao <bingz@nvidia.com>
---
 drivers/common/mlx5/mlx5_common_utils.h | 2 +-
 drivers/common/mlx5/mlx5_prm.h          | 4 ++--
 drivers/net/mlx5/mlx5.c                 | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/common/mlx5/mlx5_common_utils.h b/drivers/common/mlx5/mlx5_common_utils.h
index ae15119a33..6db0105c53 100644
--- a/drivers/common/mlx5/mlx5_common_utils.h
+++ b/drivers/common/mlx5/mlx5_common_utils.h
@@ -131,7 +131,7 @@ struct mlx5_list_inconst {
  * For huge amount of entries, please consider hash list.
  *
  */
-struct mlx5_list {
+struct __rte_aligned(16) mlx5_list {
 	struct mlx5_list_const l_const;
 	struct mlx5_list_inconst l_inconst;
 };
diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index 0875256e36..79533ff35a 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -923,7 +923,7 @@ struct mlx5_modification_cmd {
 			unsigned int field:12;
 			unsigned int action_type:4;
 		};
-	};
+	} __rte_packed;
 	union {
 		uint32_t data1;
 		uint8_t data[4];
@@ -934,7 +934,7 @@ struct mlx5_modification_cmd {
 			unsigned int dst_field:12;
 			unsigned int rsvd4:4;
 		};
-	};
+	} __rte_packed;
 };

 typedef uint64_t u64;
diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
index 25182bce39..584a51b393 100644
--- a/drivers/net/mlx5/mlx5.c
+++ b/drivers/net/mlx5/mlx5.c
@@ -906,7 +906,7 @@ mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh)
 		 */
 		case MLX5_IPOOL_MLX5_FLOW:
 			cfg.size = sh->config.dv_flow_en ?
-				sizeof(struct mlx5_flow_handle) :
+				RTE_ALIGN_MUL_CEIL(sizeof(struct mlx5_flow_handle), 8) :
 				MLX5_FLOW_HANDLE_VERBS_SIZE;
 			break;
 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H)
--
2.34.1

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2024-12-06 23:26:46.500897901 +0800
+++ 0072-common-mlx5-fix-misalignment.patch	2024-12-06 23:26:44.043044827 +0800
@@ -1 +1 @@
-From 90967539d0d1afcfd5237ed85efdc430359a0e6b Mon Sep 17 00:00:00 2001
+From 83af285731ae630e8db81a4d5a3d2e93f6826726 Mon Sep 17 00:00:00 2001
@@ -4,0 +5,3 @@
+Cc: Xueming Li <xuemingl@nvidia.com>
+
+[ upstream commit 90967539d0d1afcfd5237ed85efdc430359a0e6b ]
@@ -38 +40,0 @@
-Cc: stable@dpdk.org
@@ -49 +51 @@
-index c5eff7a0bf..9139bc6829 100644
+index ae15119a33..6db0105c53 100644
@@ -62 +64 @@
-index 210158350d..2d82807bc2 100644
+index 0875256e36..79533ff35a 100644
@@ -65 +67 @@
-@@ -941,7 +941,7 @@ struct mlx5_modification_cmd {
+@@ -923,7 +923,7 @@ struct mlx5_modification_cmd {
@@ -74 +76 @@
-@@ -952,7 +952,7 @@ struct mlx5_modification_cmd {
+@@ -934,7 +934,7 @@ struct mlx5_modification_cmd {
@@ -84 +86 @@
-index 52b90e6ff3..6e4473e2f4 100644
+index 25182bce39..584a51b393 100644
@@ -87 +89 @@
-@@ -907,7 +907,7 @@ mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh)
+@@ -906,7 +906,7 @@ mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh)