patch 'net/mlx5: fix default RSS flows creation order' has been queued to stable release 23.11.3

[Xueming Li <xuemingl@nvidia.com>]

Hi,

FYI, your patch has been queued to stable release 23.11.3

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 12/10/24. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://git.dpdk.org/dpdk-stable/log/?h=23.11-staging

This queued commit can be viewed at:
https://git.dpdk.org/dpdk-stable/commit/?h=23.11-staging&id=8db2e5cda6bfbea1ff3c75d4855c4488c2d0dc74

Thanks.

Xueming Li <xuemingl@nvidia.com>

---
From 8db2e5cda6bfbea1ff3c75d4855c4488c2d0dc74 Mon Sep 17 00:00:00 2001
From: Bing Zhao <bingz@nvidia.com>
Date: Wed, 13 Nov 2024 09:19:52 +0200
Subject: [PATCH] net/mlx5: fix default RSS flows creation order
Cc: Xueming Li <xuemingl@nvidia.com>

[ upstream commit 9a66bb734e1311bcc2bf3b286f7ab6d28975c5c7 ]

In both SWS and HWS mode, default ingress RSS flows are always
created via the driver on the root table. In the current driver,
the first created flow rules will be matched firstly when:
  1. >= 2 rules can be matched on the root table.
  2. the rules have the same priority.

All MC / BC flow rules would have the same priority and discard
the input priority from the user space in the driver. All rules have
a fixed priority 32 when the Ethernet destination MAC is a MC or BC
address.

In SWS non-template API, all the device rules are added into the list
and applied in a reverse order.

This patch syncs default flow rule creation order between SWS and HWS.
The order should be:
  1. IPv4(6) + TCP/UDP, if required.
  2. IPv4(6) only, if required.
  3. None IP traffic.

Fixes: 9fa7c1cddb85 ("net/mlx5: create control flow rules with HWS")

Signed-off-by: Bing Zhao <bingz@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
---
 drivers/net/mlx5/mlx5_flow.h    | 8 ++++----
 drivers/net/mlx5/mlx5_flow_hw.c | 2 +-
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index afb3c3b72f..01f0eab1fa 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -2443,13 +2443,13 @@ enum mlx5_flow_ctrl_rx_eth_pattern_type {

 /* All types of RSS actions used in control flow rules. */
 enum mlx5_flow_ctrl_rx_expanded_rss_type {
-	MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_NON_IP = 0,
-	MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4,
+	MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_UDP = 0,
+	MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_TCP,
 	MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_UDP,
 	MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4_TCP,
 	MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6,
-	MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_UDP,
-	MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV6_TCP,
+	MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_IPV4,
+	MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_NON_IP,
 	MLX5_FLOW_HW_CTRL_RX_EXPANDED_RSS_MAX,
 };

diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index 31e11763db..3dc26d5a0b 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -12812,7 +12812,7 @@ mlx5_flow_hw_ctrl_flows(struct rte_eth_dev *dev, uint32_t flags)
 	struct mlx5_priv *priv = dev->data->dev_private;
 	struct mlx5_flow_hw_ctrl_rx *hw_ctrl_rx;
 	unsigned int i;
-	unsigned int j;
+	int j;
 	int ret = 0;

 	RTE_SET_USED(priv);
--
2.34.1

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2024-12-06 23:26:46.539518101 +0800
+++ 0073-net-mlx5-fix-default-RSS-flows-creation-order.patch	2024-12-06 23:26:44.063044827 +0800
@@ -1 +1 @@
-From 9a66bb734e1311bcc2bf3b286f7ab6d28975c5c7 Mon Sep 17 00:00:00 2001
+From 8db2e5cda6bfbea1ff3c75d4855c4488c2d0dc74 Mon Sep 17 00:00:00 2001
@@ -4,0 +5,3 @@
+Cc: Xueming Li <xuemingl@nvidia.com>
+
+[ upstream commit 9a66bb734e1311bcc2bf3b286f7ab6d28975c5c7 ]
@@ -27 +29,0 @@
-Cc: stable@dpdk.org
@@ -37 +39 @@
-index a56e8be97e..bcc2782460 100644
+index afb3c3b72f..01f0eab1fa 100644
@@ -40 +42 @@
-@@ -2916,13 +2916,13 @@ enum mlx5_flow_ctrl_rx_eth_pattern_type {
+@@ -2443,13 +2443,13 @@ enum mlx5_flow_ctrl_rx_eth_pattern_type {
@@ -59 +61 @@
-index 6ad98d40f7..50dbaa27ab 100644
+index 31e11763db..3dc26d5a0b 100644
@@ -62 +64 @@
-@@ -16164,7 +16164,7 @@ mlx5_flow_hw_ctrl_flows(struct rte_eth_dev *dev, uint32_t flags)
+@@ -12812,7 +12812,7 @@ mlx5_flow_hw_ctrl_flows(struct rte_eth_dev *dev, uint32_t flags)