From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mails.dpdk.org (mails.dpdk.org [217.70.189.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0BB0A45E41 for ; Sat, 7 Dec 2024 09:09:35 +0100 (CET) Received: from mails.dpdk.org (localhost [127.0.0.1]) by mails.dpdk.org (Postfix) with ESMTP id 024F740281; Sat, 7 Dec 2024 09:09:35 +0100 (CET) Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2056.outbound.protection.outlook.com [40.107.94.56]) by mails.dpdk.org (Postfix) with ESMTP id 2995F40281 for ; Sat, 7 Dec 2024 09:09:33 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=H1QsAheySZFhrH27rNh0W1Iu84yO3BDLPvZlUYGjgpxM714UqoahOxq+G6PHYXHEzqvRdstb4Y2+expp+4ZRasyR5M5QcAXHAvq6aURrCy+Ox3fMEh9+RRj1cn8HNQQK1pfC1/Fh9yYsY7qv3m4cwFZEX8pTZIfzDY5O6WeGTVfxOIwW6O/XRNOQKGCJce69lIbVsLNaJRHh3dXp1Soh44HMuGavyRR7es53BD+VkIP9hsUfcRMjPk2feGHiBKHYzmShU1GWejyoFXiQfFdk7SqbDkFutl5eFMQi4XN1ODnVsQBSHnY1XfelpNzT2pSiMafzywNGwhwqcy7CFzXF4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=mgliPiAxKkcJgL4gRoebOwvksPJEYw33jzQ3QdIKLck=; b=o+Qw8fs2IDsbhujwnNouDCOfws+VLTIOMMOQpNWKsDfVlGQIgNLAXqruP8LDGNgDLsiqtOMk2Zf30Qk3txFiBiRsQS4MnquRcSxx6tFYRv7DxySksBLoNRtwBmHS0311xX6k9NSNd8Itsl/LSaCNh53v4tYiP+vWsvEWrMxWsFZ2fqSoZydzgadDC/KtDElZZDgfKYTUTi9IpMF9azUqeG5KNc3rA7zc0AyY0mXboBXIy3B5CCjRlYdIrwuA23sIwyE+s8fyZYK2LCrNBPPsGLwWgSAwV5ibrzUdAHMJfBpEp3xzcdcjk5nWA0hM7e/9h+zO6mnur5sIBIyPWHHlXA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 216.228.117.161) smtp.rcpttodomain=trustnetic.com smtp.mailfrom=nvidia.com; dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=mgliPiAxKkcJgL4gRoebOwvksPJEYw33jzQ3QdIKLck=; b=U/4kjHX8EyvGc/oN1aINd62vjNYildMJZj9wak6mPV6ilxman0XzBPOoMDQPvS38ZUdIYIpVJZg+Wn0OB9urRhn2MHj5+uPL/Pe2V49wXu4jyNb7c0wtwGBADytDMzMIHgsl863jKED6MwKOhTNpnStIyIKYUmDQyo+nf8euBTMZvCQzZ4tJ+6aVx9x4lcjrGR2dsrFwr0SMBAQgU7Qhrj2pOu3fTPNKHmLKC+uO+3j0uLXUaNHAdIpeKA/rKez+YSrsiYXxyRD2lGAwlFa4EKtJ6pAOkV9TUeaarWN0+FW/gLKhNCPEniVmlhLnrJTmtp4hiZgZ0Ms73RG6l1ExBA== Received: from BN9P220CA0003.NAMP220.PROD.OUTLOOK.COM (2603:10b6:408:13e::8) by PH7PR12MB5594.namprd12.prod.outlook.com (2603:10b6:510:134::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8207.18; Sat, 7 Dec 2024 08:09:26 +0000 Received: from BL02EPF00021F6B.namprd02.prod.outlook.com (2603:10b6:408:13e:cafe::5f) by BN9P220CA0003.outlook.office365.com (2603:10b6:408:13e::8) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.8230.12 via Frontend Transport; Sat, 7 Dec 2024 08:09:25 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 216.228.117.161) smtp.mailfrom=nvidia.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BL02EPF00021F6B.mail.protection.outlook.com (10.167.249.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8230.7 via Frontend Transport; Sat, 7 Dec 2024 08:09:25 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Sat, 7 Dec 2024 00:09:17 -0800 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Sat, 7 Dec 2024 00:09:15 -0800 From: Xueming Li To: Jiawen Wu CC: Xueming Li , dpdk stable Subject: patch 'net/txgbe: fix a mass of interrupts' has been queued to stable release 23.11.3 Date: Sat, 7 Dec 2024 16:00:44 +0800 Message-ID: <20241207080055.488538-87-xuemingl@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241207080055.488538-1-xuemingl@nvidia.com> References: <20241111062847.216344-122-xuemingl@nvidia.com> <20241207080055.488538-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF00021F6B:EE_|PH7PR12MB5594:EE_ X-MS-Office365-Filtering-Correlation-Id: 37429b3a-b879-4321-febd-08dd169676f3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|82310400026|36860700013|376014|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?sj0CsASyijQ19FT/+YyKR529ZMzBagDdQWqhkaonV4j1SVUZgvvFNbfajPSq?= =?us-ascii?Q?VqoVkkbly8rxn2AXCMymsp7uR/d0SWXthlpn5JawPgJzbpS3dCMI0l4pH6dG?= =?us-ascii?Q?IwuoJ/MSREFgOafIjr+5cXrvLlIdelNbA/KFPn7koJod9STE7ah13u/8U1sT?= =?us-ascii?Q?dP0cKi4VMTNOh8gi8+PLk9u6Er1IAuRBaWYhN5mQpV1QCwQETSG/Ym3K2mm4?= =?us-ascii?Q?vpgsUufW5ncNyeZ7wlgY/LGAchy5gVeex+1tDTP9RgvhVUqnbMWM8lN8xLqG?= =?us-ascii?Q?KwbzB4Kn1MdUfHSQRueldZeIah4UTEDP0ocu9JniURx3j01pf6otiTS6ejMe?= =?us-ascii?Q?AlRy8vdB7Ij4vNj33NMnW1AzJi4Z9LUzbcGurJnHTGQ1a1jmEXTs72kX2VRA?= =?us-ascii?Q?887WIJYlKrI5ntmhyDMi46hrKJOia3cdIM/FjaCsAyOf6eEPwq19nnzJZCqA?= =?us-ascii?Q?QO1f8F075gibpOLJn5ots30CMymOcrwmDF4Acr+GKMNQ/vCPHwJWsO7nlL5R?= =?us-ascii?Q?7pCajdARu02HD8WFYYb5HlXsql/hCck2UWrZrxNH6Ag8seGYbGnZL39C0T60?= =?us-ascii?Q?vqWSe8ODuAWqPikAg33og3y7KURE9f11jtsoKamWOEQC/sgfycf2vys72uv8?= =?us-ascii?Q?NWrJ14xeR+B7rnwHGnrRY+Wd5SqiC4QP8RyjYfd3bpg3hlMwh3vyn33mFcG+?= =?us-ascii?Q?GoZlhjR88y+BVYSBayta50MQMQM80/SdLO1C9t8wcMZjf38x2BYADnV7t1Ie?= =?us-ascii?Q?u4tTCASrfLHYdCp0nilqe/6MnCAgkz1SrOMIWRWYUQetBprh206qqEgmMiLZ?= =?us-ascii?Q?T48fJ2jzjW/7AJDUApXBpU75elHaHC2qqyMxT4IJjfTiXcgrPOkjPhfnU0bX?= =?us-ascii?Q?BqKBpSOPnnGi3kzcyFrL0L+rJBBI6ZniSvyWHNZzwN3w5cqEFnDejfYZ64TA?= =?us-ascii?Q?oEEKRNZNJoWnbFyqfC6B3jWleaf1FgLC2KgZofzQaTSQaOMy9Zsfyc+em0Dv?= =?us-ascii?Q?FgggYrXzR4kKjGRYOOsHgfwQYMzB+w+zuLEcn8inw4iwZW0d6/YtrPYfXvbO?= =?us-ascii?Q?T5xStg8XPDY76evQi0C/OB8G5qS5qX0e9Ln/l9VkOjHY2sqeVAl5qhdhfICh?= =?us-ascii?Q?ceec+uN1NY0pj+RqUyxHdSgczDCOAdL+SwA7yJfa29f+dyVBGf1N9CZagfSz?= =?us-ascii?Q?3xCcUJ2kMxa3CKaupMi9AtNCage/J59BBZ5zFmXU1VHNgMidlxIYMRTHwYM0?= =?us-ascii?Q?B37k4pxfe4JoQVJ5C7vwJtgClpRgVCR9yO5ZpV7eWBbD/fOtFN8i5nVbWj2Y?= =?us-ascii?Q?WRubogR36HxPlcqAi+VyTUvINK8WiT0uV8k+PzGXHz/Bk294HE5GfQPez0eN?= =?us-ascii?Q?b5v3D70RS2M+ItqxzYHj+J1dj2nh/fRDviFxnpW+ekCNKrBsstnZTfCjHj8+?= =?us-ascii?Q?WWzVTzW+dm6+R6NFcOiK2rmEbXBxPEDb?= X-Forefront-Antispam-Report: CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(1800799024)(82310400026)(36860700013)(376014)(7053199007); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Dec 2024 08:09:25.1210 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 37429b3a-b879-4321-febd-08dd169676f3 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF00021F6B.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5594 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 23.11.3 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 12/10/24. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://git.dpdk.org/dpdk-stable/log/?h=23.11-staging This queued commit can be viewed at: https://git.dpdk.org/dpdk-stable/commit/?h=23.11-staging&id=6262d28b1f89515a423f33d06c1d908a65bf6bc3 Thanks. Xueming Li --- >From 6262d28b1f89515a423f33d06c1d908a65bf6bc3 Mon Sep 17 00:00:00 2001 From: Jiawen Wu Date: Fri, 15 Nov 2024 16:33:36 +0800 Subject: [PATCH] net/txgbe: fix a mass of interrupts Cc: Xueming Li [ upstream commit 916aa13f4a198aebf5383f9680cb5cd527518f2c ] Since firmware version 0x20010, GPIO interrupt enable is set to 0xd by default, which means enable bit 0 'tx_fault'. And GPIO interrupt polarity is set to 0xd by default too, which means these interrupts are rising-edge sensitive. So when unplug the SFP module, GPIO line 0 'tx_fault' is 0 -> 1 triggers the interrupt. However, the interrupt is not cleared. And GPIO interrupt mask is enabled and disabled to trigger the MISC interrupt repeatedly. Since this 'tx_fault' interrupt does not make much sense, simply clear it to fix the issue. Fixes: 12011b11a3d6 ("net/txgbe: adapt to MNG veto bit setting") Signed-off-by: Jiawen Wu --- drivers/net/txgbe/txgbe_ethdev.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c index 9b44f11465..25b657d0ff 100644 --- a/drivers/net/txgbe/txgbe_ethdev.c +++ b/drivers/net/txgbe/txgbe_ethdev.c @@ -1553,6 +1553,9 @@ static void txgbe_reinit_gpio_intr(struct txgbe_hw *hw) wr32(hw, TXGBE_GPIOINTMASK, 0xFF); reg = rd32(hw, TXGBE_GPIORAWINTSTAT); + if (reg & TXGBE_GPIOBIT_0) + wr32(hw, TXGBE_GPIOEOI, TXGBE_GPIOBIT_0); + if (reg & TXGBE_GPIOBIT_2) wr32(hw, TXGBE_GPIOEOI, TXGBE_GPIOBIT_2); @@ -2776,6 +2779,8 @@ txgbe_dev_sfp_event(struct rte_eth_dev *dev) wr32(hw, TXGBE_GPIOINTMASK, 0xFF); reg = rd32(hw, TXGBE_GPIORAWINTSTAT); + if (reg & TXGBE_GPIOBIT_0) + wr32(hw, TXGBE_GPIOEOI, TXGBE_GPIOBIT_0); if (reg & TXGBE_GPIOBIT_2) { wr32(hw, TXGBE_GPIOEOI, TXGBE_GPIOBIT_2); rte_eal_alarm_set(1000 * 100, txgbe_dev_detect_sfp, dev); -- 2.34.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2024-12-06 23:26:46.964933206 +0800 +++ 0086-net-txgbe-fix-a-mass-of-interrupts.patch 2024-12-06 23:26:44.103044826 +0800 @@ -1 +1 @@ -From 916aa13f4a198aebf5383f9680cb5cd527518f2c Mon Sep 17 00:00:00 2001 +From 6262d28b1f89515a423f33d06c1d908a65bf6bc3 Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Xueming Li + +[ upstream commit 916aa13f4a198aebf5383f9680cb5cd527518f2c ] @@ -19 +21,0 @@ -Cc: stable@dpdk.org @@ -27 +29 @@ -index a956216abb..ea9faba2c0 100644 +index 9b44f11465..25b657d0ff 100644 @@ -30 +32 @@ -@@ -1555,6 +1555,9 @@ static void txgbe_reinit_gpio_intr(struct txgbe_hw *hw) +@@ -1553,6 +1553,9 @@ static void txgbe_reinit_gpio_intr(struct txgbe_hw *hw) @@ -40 +42 @@ -@@ -2796,6 +2799,8 @@ txgbe_dev_sfp_event(struct rte_eth_dev *dev) +@@ -2776,6 +2779,8 @@ txgbe_dev_sfp_event(struct rte_eth_dev *dev)