patch 'net/mlx5: fix GRE flow match with SWS' has been queued to stable release 23.11.4

[Xueming Li <xuemingl@nvidia.com>]

Hi,

FYI, your patch has been queued to stable release 23.11.4

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
Please shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://git.dpdk.org/dpdk-stable/log/?h=23.11-staging

This queued commit can be viewed at:
https://git.dpdk.org/dpdk-stable/commit/?h=23.11-staging&id=b81990ea04c23689ce76df612e7ada1eb9c6de76

Thanks.

Xueming Li <xuemingl@nvidia.com>

---
From b81990ea04c23689ce76df612e7ada1eb9c6de76 Mon Sep 17 00:00:00 2001
From: Maayan Kashani <mkashani@nvidia.com>
Date: Tue, 28 Jan 2025 09:59:30 +0200
Subject: [PATCH] net/mlx5: fix GRE flow match with SWS
Cc: Xueming Li <xuemingl@nvidia.com>

[ upstream commit 05db99c117e36c0cd28cda8f558309efd20055da ]

The previous GRE fix was meant to handle HWS behavior
and changed the behavior for SWS causing degradation.

After the previous fix, in case of an empty GRE match,
GRE mask was initialized with protocol full mask,
Instead of the empty mask with protocol mask equals zero.

The current fix handles the SWS case as before the GRE fix,
and HWS according to the latest fix.
Also, combined common logic.

Fixes: 25ab2cbba31d ("net/mlx5: fix GRE flow item translation for root table")

Signed-off-by: Maayan Kashani <mkashani@nvidia.com>
Acked-by: Bing Zhao <bingz@nvidia.com>
---
 drivers/net/mlx5/mlx5_flow_dv.c | 27 +++++++++++++++------------
 1 file changed, 15 insertions(+), 12 deletions(-)

diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 09c7068339..80edb4e966 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -9476,23 +9476,26 @@ flow_dv_translate_item_gre(void *key, const struct rte_flow_item *item,
 	} gre_crks_rsvd0_ver_m, gre_crks_rsvd0_ver_v;
 	uint16_t protocol_m, protocol_v;

-	if (key_type & MLX5_SET_MATCHER_M) {
+	/* Common logic to SWS/HWS */
+	if (key_type & MLX5_SET_MATCHER_M)
 		MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol, 0xff);
+	else
+		MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
+			IPPROTO_GRE);
+	/* HWS mask logic only */
+	if (key_type & MLX5_SET_MATCHER_HS_M) {
 		if (!gre_m)
 			gre_m = &rte_flow_item_gre_mask;
 		gre_v = gre_m;
-	} else {
-		MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
-			 IPPROTO_GRE);
-		if (!gre_v) {
-			gre_v = &empty_gre;
-			gre_m = &empty_gre;
-		} else if (!gre_m) {
-			gre_m = &rte_flow_item_gre_mask;
-		}
-		if (key_type == MLX5_SET_MATCHER_HS_V)
-			gre_m = gre_v;
+	} else if (!gre_v) {
+		gre_v = &empty_gre;
+		gre_m = &empty_gre;
+	} else if (!gre_m) {
+		gre_m = &rte_flow_item_gre_mask;
 	}
+	/* SWS logic only */
+	if (key_type & MLX5_SET_MATCHER_SW_M)
+		gre_v = gre_m;
 	gre_crks_rsvd0_ver_m.value = rte_be_to_cpu_16(gre_m->c_rsvd0_ver);
 	gre_crks_rsvd0_ver_v.value = rte_be_to_cpu_16(gre_v->c_rsvd0_ver);
 	MLX5_SET(fte_match_set_misc, misc_v, gre_c_present,
--
2.34.1

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2025-02-18 19:39:02.306600159 +0800
+++ 0044-net-mlx5-fix-GRE-flow-match-with-SWS.patch	2025-02-18 19:39:00.608244051 +0800
@@ -1 +1 @@
-From 05db99c117e36c0cd28cda8f558309efd20055da Mon Sep 17 00:00:00 2001
+From b81990ea04c23689ce76df612e7ada1eb9c6de76 Mon Sep 17 00:00:00 2001
@@ -4,0 +5,3 @@
+Cc: Xueming Li <xuemingl@nvidia.com>
+
+[ upstream commit 05db99c117e36c0cd28cda8f558309efd20055da ]
@@ -18 +20,0 @@
-Cc: stable@dpdk.org
@@ -27 +29 @@
-index 41ebe0b61a..633c41e358 100644
+index 09c7068339..80edb4e966 100644
@@ -30 +32 @@
-@@ -9839,23 +9839,26 @@ flow_dv_translate_item_gre(void *key, const struct rte_flow_item *item,
+@@ -9476,23 +9476,26 @@ flow_dv_translate_item_gre(void *key, const struct rte_flow_item *item,