patches for DPDK stable branches
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From: Kevin Traynor <ktraynor@redhat.com>
To: Maayan Kashani <mkashani@nvidia.com>
Cc: Bing Zhao <bingz@nvidia.com>, dpdk stable <stable@dpdk.org>
Subject: patch 'net/mlx5: fix flow matching GENEVE options' has been queued to stable release 24.11.2
Date: Mon, 24 Mar 2025 16:16:24 +0000	[thread overview]
Message-ID: <20250324161731.63950-17-ktraynor@redhat.com> (raw)
In-Reply-To: <20250324161731.63950-1-ktraynor@redhat.com>

Hi,

FYI, your patch has been queued to stable release 24.11.2

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 03/28/25. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://github.com/kevintraynor/dpdk-stable

This queued commit can be viewed at:
https://github.com/kevintraynor/dpdk-stable/commit/44d0ab5afc575e375f44ab75a0b6b380aba605af

Thanks.

Kevin

---
From 44d0ab5afc575e375f44ab75a0b6b380aba605af Mon Sep 17 00:00:00 2001
From: Maayan Kashani <mkashani@nvidia.com>
Date: Tue, 4 Mar 2025 09:56:54 +0200
Subject: [PATCH] net/mlx5: fix flow matching GENEVE options

[ upstream commit fdca628a3e22080a27ff5cd166b2e6537f3cf464 ]

For non-template API on top of HWS,
geneve options were missing a parser and therefore it failed.
In template API it geneve options is configured by the user
using mlx5 set/apply tlv_options commands.

To support hybrid mode, if no parser exists,
added inner configuration of geneve parser, else,
in debug mode, check if the geneve option needed exist in
current parser configured.
In release mode, assume the option exist in current configured parser.

Updated needed configuration for geneve options in doc.

Fixes: e38776c36c8a ("net/mlx5: introduce HWS for non-template flow API")

Signed-off-by: Maayan Kashani <mkashani@nvidia.com>
Acked-by: Bing Zhao <bingz@nvidia.com>
---
 doc/guides/nics/mlx5.rst            |  5 +++
 drivers/net/mlx5/mlx5_flow.h        | 17 +++++++
 drivers/net/mlx5/mlx5_flow_dv.c     | 69 ++++++++++++++++++++++++++++-
 drivers/net/mlx5/mlx5_flow_geneve.c |  2 +-
 drivers/net/mlx5/mlx5_flow_hw.c     |  6 +--
 5 files changed, 93 insertions(+), 6 deletions(-)

diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst
index c9c23eedb2..896f9a0027 100644
--- a/doc/guides/nics/mlx5.rst
+++ b/doc/guides/nics/mlx5.rst
@@ -280,4 +280,9 @@ Limitations
     d. Only in transfer (switchdev) mode.
 
+  - When using synchronous flow API,
+    the following limitations and considerations apply:
+
+    - Geneve options is supported when ``FLEX_PARSER_PROFILE_ENABLE`` = 0 (default).
+
 - When using Verbs flow engine (``dv_flow_en`` = 0), flow pattern without any
   specific VLAN will match for VLAN packets as well:
diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h
index 9c8892b194..72f6cf6a32 100644
--- a/drivers/net/mlx5/mlx5_flow.h
+++ b/drivers/net/mlx5/mlx5_flow.h
@@ -2158,4 +2158,21 @@ flow_hw_get_port_id_from_ctx(void *dr_ctx, uint32_t *port_val)
 }
 
+/**
+ * Get GENEVE TLV option matching to given type and class.
+ *
+ * @param priv
+ *   Pointer to port's private data.
+ * @param type
+ *   GENEVE option type.
+ * @param class
+ *   GENEVE option class.
+ *
+ * @return
+ *   Pointer to option structure if exist, NULL otherwise and rte_errno is set.
+ */
+struct mlx5_geneve_tlv_option *
+mlx5_geneve_tlv_option_get(const struct mlx5_priv *priv, uint8_t type,
+			    uint16_t class);
+
 /**
  * Get GENEVE TLV option FW information according type and class.
diff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c
index 633c41e358..a4a3552386 100644
--- a/drivers/net/mlx5/mlx5_flow_dv.c
+++ b/drivers/net/mlx5/mlx5_flow_dv.c
@@ -14447,4 +14447,62 @@ flow_dv_translate_items(struct rte_eth_dev *dev,
 }
 
+static int
+flow_dv_translate_items_geneve_opt_nta(struct rte_eth_dev *dev,
+				   const struct rte_flow_item *items,
+				   struct mlx5_flow_attr *attr,
+				   struct rte_flow_error *error)
+{
+	rte_be32_t geneve_mask = 0xffffffff;
+	struct rte_pmd_mlx5_geneve_tlv geneve_tlv = {
+		/* Take from item spec, if changed, destroy and add new parser. */
+		.option_class			= 0,
+		/* Take from item spec, if changed, destroy and add new parser. */
+		.option_type			= 0,
+		/* 1DW is supported. */
+		.option_len			= 1,
+		.match_on_class_mode		= 1,
+		.offset				= 0,
+		.sample_len			= 1,
+		.match_data_mask		= &geneve_mask
+	};
+	const struct rte_flow_item_geneve_opt *geneve_opt_v = items->spec;
+	const struct rte_flow_item_geneve_opt *geneve_opt_m = items->mask;
+	void *geneve_parser;
+	struct mlx5_priv *priv = dev->data->dev_private;
+#ifdef RTE_LIBRTE_MLX5_DEBUG
+	struct mlx5_geneve_tlv_option *option;
+#endif
+
+	/* option length is not as supported. */
+	if ((geneve_opt_v->option_len & geneve_opt_m->option_len) > geneve_tlv.option_len)
+		return rte_flow_error_set(error, ENOTSUP,
+			RTE_FLOW_ERROR_TYPE_ITEM, items,
+			" GENEVE OPT length is not supported ");
+	geneve_tlv.option_class = geneve_opt_v->option_class & geneve_opt_m->option_class;
+	geneve_tlv.option_type = geneve_opt_v->option_type & geneve_opt_m->option_type;
+	/* if parser doesn't exist */
+	if (!priv->tlv_options) {
+		/* Create a GENEVE option parser. */
+		geneve_parser = mlx5_geneve_tlv_parser_create(attr->port_id,
+						&geneve_tlv, 1);
+		if (!geneve_parser)
+			return rte_flow_error_set(error, EINVAL,
+				RTE_FLOW_ERROR_TYPE_ITEM, items,
+				" GENEVE OPT parser creation failed ");
+#ifdef RTE_LIBRTE_MLX5_DEBUG
+	} else {
+		/* Check if option exist in current parser. */
+		option = mlx5_geneve_tlv_option_get(priv,
+						geneve_tlv.option_type,
+						geneve_tlv.option_class);
+		if (!option)
+			return rte_flow_error_set(error, EINVAL,
+				RTE_FLOW_ERROR_TYPE_ITEM, items,
+				" GENEVE OPT configured does not match this rule class/type");
+#endif
+	}
+	return 0;
+}
+
 /**
  * Fill the flow matcher with DV spec for items supported in non template mode.
@@ -14471,4 +14529,5 @@ flow_dv_translate_items_nta(struct rte_eth_dev *dev,
 			struct mlx5_dv_matcher_workspace *wks,
 			void *key, uint32_t key_type,
+			struct mlx5_flow_attr *attr,
 			struct rte_flow_error *error)
 {
@@ -14491,4 +14550,10 @@ flow_dv_translate_items_nta(struct rte_eth_dev *dev,
 		wks->last_item = tunnel ? MLX5_FLOW_ITEM_INNER_FLEX : MLX5_FLOW_ITEM_OUTER_FLEX;
 		break;
+	case RTE_FLOW_ITEM_TYPE_GENEVE_OPT:
+		ret = flow_dv_translate_items_geneve_opt_nta(dev, items, attr, error);
+		if (ret)
+			return ret;
+		wks->last_item = MLX5_FLOW_LAYER_GENEVE_OPT;
+		break;
 	default:
 		ret = flow_dv_translate_items(dev, items, wks, key, key_type,  error);
@@ -14561,10 +14626,10 @@ __flow_dv_translate_items_hws(const struct rte_flow_item *items,
 		if (nt_flow) {
 			ret = flow_dv_translate_items_nta(&rte_eth_devices[attr->port_id],
-							  items, &wks, key, key_type,  NULL);
+							  items, &wks, key, key_type, attr, error);
 			if (ret)
 				goto exit;
 		} else {
 			ret = flow_dv_translate_items(&rte_eth_devices[attr->port_id],
-						      items, &wks, key, key_type,  NULL);
+						      items, &wks, key, key_type, error);
 			if (ret)
 				goto exit;
diff --git a/drivers/net/mlx5/mlx5_flow_geneve.c b/drivers/net/mlx5/mlx5_flow_geneve.c
index d8086d333f..6bf53e1270 100644
--- a/drivers/net/mlx5/mlx5_flow_geneve.c
+++ b/drivers/net/mlx5/mlx5_flow_geneve.c
@@ -98,5 +98,5 @@ option_match_type_and_class(uint8_t type, uint16_t class,
  *   Pointer to option structure if exist, NULL otherwise and rte_errno is set.
  */
-static struct mlx5_geneve_tlv_option *
+struct mlx5_geneve_tlv_option *
 mlx5_geneve_tlv_option_get(const struct mlx5_priv *priv, uint8_t type,
 			   uint16_t class)
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index 07037d49cb..126f0475d5 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -13792,7 +13792,7 @@ flow_hw_create_flow(struct rte_eth_dev *dev, enum mlx5_flow_type type,
 	(*flow)->nt_rule = true;
 	(*flow)->nt2hws->matcher = &matcher;
-	ret = flow_dv_translate_items_hws(items, &flow_attr, &matcher.mask.buf,
-					MLX5_SET_MATCHER_HS_M, NULL,
-					NULL, error);
+	ret = __flow_dv_translate_items_hws(items, &flow_attr, &matcher.mask.buf,
+					    MLX5_SET_MATCHER_HS_M, NULL,
+					    NULL, true, error);
 
 	if (ret)
-- 
2.48.1

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2025-03-24 16:15:15.423845567 +0000
+++ 0017-net-mlx5-fix-flow-matching-GENEVE-options.patch	2025-03-24 16:15:14.804735721 +0000
@@ -1 +1 @@
-From fdca628a3e22080a27ff5cd166b2e6537f3cf464 Mon Sep 17 00:00:00 2001
+From 44d0ab5afc575e375f44ab75a0b6b380aba605af Mon Sep 17 00:00:00 2001
@@ -5,0 +6,2 @@
+[ upstream commit fdca628a3e22080a27ff5cd166b2e6537f3cf464 ]
+
@@ -20 +21,0 @@
-Cc: stable@dpdk.org
@@ -33 +34 @@
-index b45abb6d95..afb19241dc 100644
+index c9c23eedb2..896f9a0027 100644
@@ -36,2 +37,2 @@
-@@ -294,4 +294,9 @@ Limitations
-     - RTE_FLOW_ITEM_TYPE_MPLS matching is not supported on group 0.
+@@ -280,4 +280,9 @@ Limitations
+     d. Only in transfer (switchdev) mode.
@@ -47 +48 @@
-index e5245edd46..a5bde158ca 100644
+index 9c8892b194..72f6cf6a32 100644
@@ -50 +51 @@
-@@ -2159,4 +2159,21 @@ flow_hw_get_port_id_from_ctx(void *dr_ctx, uint32_t *port_val)
+@@ -2158,4 +2158,21 @@ flow_hw_get_port_id_from_ctx(void *dr_ctx, uint32_t *port_val)
@@ -73 +74 @@
-index 61d3101ce8..c77041317b 100644
+index 633c41e358..a4a3552386 100644
@@ -76 +77 @@
-@@ -14449,4 +14449,62 @@ flow_dv_translate_items(struct rte_eth_dev *dev,
+@@ -14447,4 +14447,62 @@ flow_dv_translate_items(struct rte_eth_dev *dev,
@@ -139 +140 @@
-@@ -14473,4 +14531,5 @@ flow_dv_translate_items_nta(struct rte_eth_dev *dev,
+@@ -14471,4 +14529,5 @@ flow_dv_translate_items_nta(struct rte_eth_dev *dev,
@@ -145 +146 @@
-@@ -14493,4 +14552,10 @@ flow_dv_translate_items_nta(struct rte_eth_dev *dev,
+@@ -14491,4 +14550,10 @@ flow_dv_translate_items_nta(struct rte_eth_dev *dev,
@@ -156 +157 @@
-@@ -14563,10 +14628,10 @@ __flow_dv_translate_items_hws(const struct rte_flow_item *items,
+@@ -14561,10 +14626,10 @@ __flow_dv_translate_items_hws(const struct rte_flow_item *items,
@@ -181 +182 @@
-index 22778310b0..6254857301 100644
+index 07037d49cb..126f0475d5 100644
@@ -184 +185 @@
-@@ -14036,7 +14036,7 @@ flow_hw_create_flow(struct rte_eth_dev *dev, enum mlx5_flow_type type,
+@@ -13792,7 +13792,7 @@ flow_hw_create_flow(struct rte_eth_dev *dev, enum mlx5_flow_type type,


  parent reply	other threads:[~2025-03-24 16:20 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-24 16:16 patch 'doc: fix year of final LTS release' " Kevin Traynor
2025-03-24 16:16 ` patch 'net/bnxt: fix epoch bit calculation' " Kevin Traynor
2025-03-24 16:16 ` patch 'net/iavf: fix mbuf release in Arm multi-process' " Kevin Traynor
2025-03-24 16:16 ` patch 'net/ice: fix flow engines order' " Kevin Traynor
2025-03-24 16:16 ` patch 'net/ice: fix dropped packets when using VRRP' " Kevin Traynor
2025-03-24 16:16 ` patch 'net/iavf: check interrupt registration failure' " Kevin Traynor
2025-03-24 16:16 ` patch 'net/iavf: fix crash on app exit on FreeBSD' " Kevin Traynor
2025-03-24 16:16 ` patch 'net/mlx5: fix hairpin queue release' " Kevin Traynor
2025-03-24 16:16 ` patch 'net/mlx5: fix LACP packet handling in isolated mode' " Kevin Traynor
2025-03-24 16:16 ` patch 'net/mlx5/hws: fix crash using represented port without ID' " Kevin Traynor
2025-03-24 16:16 ` patch 'net/mlx5: fix non-template set VLAN VID' " Kevin Traynor
2025-03-24 16:16 ` patch 'net/mlx5: fix error info in actions construct' " Kevin Traynor
2025-03-24 16:16 ` patch 'net/mlx5/hws: fix GTP flags matching' " Kevin Traynor
2025-03-24 16:16 ` patch 'net/mlx5: fix non-template flow validation' " Kevin Traynor
2025-03-24 16:16 ` patch 'net/mlx5: fix non-template flow validation on create' " Kevin Traynor
2025-03-24 16:16 ` patch 'net/mlx5: fix flow group ID for action translation' " Kevin Traynor
2025-03-24 16:16 ` Kevin Traynor [this message]
2025-03-24 16:16 ` patch 'net/mlx5: fix IPIP tunnel verification' " Kevin Traynor
2025-03-24 16:16 ` patch 'net/mlx5: fix mark action validation in FDB mode' " Kevin Traynor
2025-03-24 16:16 ` patch 'net/mlx5: fix NAT64 register selection' " Kevin Traynor
2025-03-24 16:16 ` patch 'net/mlx5: fix GRE matching on root table' " Kevin Traynor
2025-03-24 16:16 ` patch 'common/mlx5: add device duplication function' " Kevin Traynor
2025-03-24 16:16 ` patch 'net/mlx5: fix GENEVE parser cleanup' " Kevin Traynor
2025-03-24 16:16 ` patch 'baseband/acc: fix queue setup failure clean up' " Kevin Traynor
2025-03-24 16:16 ` patch 'common/qat: fix devargs parsing' " Kevin Traynor
2025-03-24 16:16 ` patch 'dts: fix smoke tests docstring' " Kevin Traynor
2025-03-24 16:16 ` patch 'pdump: clear statistics when enabled' " Kevin Traynor
2025-03-24 16:16 ` patch 'examples/flow_filtering: fix IPv4 matching snippet' " Kevin Traynor
2025-03-24 16:16 ` patch 'examples/ipsec-secgw: fix cryptodev and eventdev IDs' " Kevin Traynor
2025-03-24 16:16 ` patch 'doc: add no-IOMMU mode in devbind tool guide' " Kevin Traynor
2025-03-24 16:16 ` patch 'eal: fix undetected NUMA nodes' " Kevin Traynor
2025-03-24 16:16 ` patch 'net/ixgbe: add checks for E610 VF' " Kevin Traynor

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