patch 'net/mlx5: fix NAT64 register selection' has been queued to stable release 24.11.2

[Kevin Traynor <ktraynor@redhat.com>]

Hi,

FYI, your patch has been queued to stable release 24.11.2

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 03/28/25. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://github.com/kevintraynor/dpdk-stable

This queued commit can be viewed at:
https://github.com/kevintraynor/dpdk-stable/commit/9ca66f3f0cbcc7d3e646e3c5f22c3b9859ad982c

Thanks.

Kevin

---
From 9ca66f3f0cbcc7d3e646e3c5f22c3b9859ad982c Mon Sep 17 00:00:00 2001
From: Dariusz Sosnowski <dsosnowski@nvidia.com>
Date: Wed, 12 Mar 2025 10:51:08 +0100
Subject: [PATCH] net/mlx5: fix NAT64 register selection

[ upstream commit f15535128617db8c1e9cad4793e7daf0d698eef9 ]

PMD statically assumed that REG_C_6 is always available for use
with NAT64 HW action.
This led to PMD configuration errors on FW versions which do not expose
that specific register.

This patch fixes that by adding a check for REG_C_6 against FW
capabilities, when registers for NAT64 are selected.

Also, if not enough registers are available, PMD will not attempt to
create NAT64 actions.

Fixes: 7a26bfec06a4 ("net/mlx5: fetch available registers for NAT64")

Signed-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
Acked-by: Bing Zhao <bingz@nvidia.com>
---
 drivers/net/mlx5/mlx5.c         | 16 +++++++++++-----
 drivers/net/mlx5/mlx5_flow_hw.c | 22 ++++++++++++++++++++--
 2 files changed, 31 insertions(+), 7 deletions(-)

diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c
index 6e4473e2f4..5616cf4011 100644
--- a/drivers/net/mlx5/mlx5.c
+++ b/drivers/net/mlx5/mlx5.c
@@ -1626,5 +1626,6 @@ mlx5_init_hws_flow_tags_registers(struct mlx5_dev_ctx_shared *sh)
 	struct mlx5_dev_registers *reg = &sh->registers;
 	uint32_t meta_mode = sh->config.dv_xmeta_en;
-	uint16_t masks = (uint16_t)sh->cdev->config.hca_attr.set_reg_c;
+	uint16_t reg_c_caps = (uint16_t)sh->cdev->config.hca_attr.set_reg_c;
+	uint16_t masks = reg_c_caps;
 	uint16_t unset = 0;
 	uint32_t i, j;
@@ -1650,9 +1651,14 @@ mlx5_init_hws_flow_tags_registers(struct mlx5_dev_ctx_shared *sh)
 	 * The other 2 registers will be fetched from right to left, at least 2
 	 * tag registers should be available.
+	 * If not enough registers are available or REG_C_6 is not supported by current FW,
+	 * NAT64 action will not be supported.
 	 */
-	MLX5_ASSERT(j >= (MLX5_FLOW_NAT64_REGS_MAX - 1));
-	reg->nat64_regs[0] = REG_C_6;
-	reg->nat64_regs[1] = reg->hw_avl_tags[j - 2];
-	reg->nat64_regs[2] = reg->hw_avl_tags[j - 1];
+	if ((reg_c_caps & RTE_BIT32(mlx5_regc_index(REG_C_6))) &&
+	    j >= MLX5_FLOW_NAT64_REGS_MAX - 1) {
+		MLX5_ASSERT(j >= (MLX5_FLOW_NAT64_REGS_MAX - 1));
+		reg->nat64_regs[0] = REG_C_6;
+		reg->nat64_regs[1] = reg->hw_avl_tags[j - 2];
+		reg->nat64_regs[2] = reg->hw_avl_tags[j - 1];
+	}
 }
 
diff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c
index 126f0475d5..5601abf90d 100644
--- a/drivers/net/mlx5/mlx5_flow_hw.c
+++ b/drivers/net/mlx5/mlx5_flow_hw.c
@@ -9500,4 +9500,17 @@ flow_hw_destroy_send_to_kernel_action(struct mlx5_priv *priv)
 }
 
+static bool
+flow_hw_should_create_nat64_actions(struct mlx5_priv *priv)
+{
+	int i;
+
+	/* Check if all registers are available. */
+	for (i = 0; i < MLX5_FLOW_NAT64_REGS_MAX; ++i)
+		if (priv->sh->registers.nat64_regs[i] == REG_NON)
+			return false;
+
+	return true;
+}
+
 static void
 flow_hw_destroy_nat64_actions(struct mlx5_priv *priv)
@@ -11966,7 +11979,12 @@ __flow_hw_configure(struct rte_eth_dev *dev,
 		goto err;
 	}
-	if (flow_hw_create_nat64_actions(priv, error))
+	if (flow_hw_should_create_nat64_actions(priv)) {
+		if (flow_hw_create_nat64_actions(priv, error))
+			goto err;
+	} else {
 		DRV_LOG(WARNING, "Cannot create NAT64 action on port %u, "
-			"please check the FW version", dev->data->port_id);
+			"please check the FW version. NAT64 will not be supported.",
+			dev->data->port_id);
+	}
 	if (_queue_attr)
 		mlx5_free(_queue_attr);
-- 
2.48.1

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2025-03-24 16:15:15.557558370 +0000
+++ 0020-net-mlx5-fix-NAT64-register-selection.patch	2025-03-24 16:15:14.834735843 +0000
@@ -1 +1 @@
-From f15535128617db8c1e9cad4793e7daf0d698eef9 Mon Sep 17 00:00:00 2001
+From 9ca66f3f0cbcc7d3e646e3c5f22c3b9859ad982c Mon Sep 17 00:00:00 2001
@@ -5,0 +6,2 @@
+[ upstream commit f15535128617db8c1e9cad4793e7daf0d698eef9 ]
+
@@ -18 +19,0 @@
-Cc: stable@dpdk.org
@@ -28 +29 @@
-index 0f49cb5e5b..e175f81031 100644
+index 6e4473e2f4..5616cf4011 100644
@@ -31 +32 @@
-@@ -1625,5 +1625,6 @@ mlx5_init_hws_flow_tags_registers(struct mlx5_dev_ctx_shared *sh)
+@@ -1626,5 +1626,6 @@ mlx5_init_hws_flow_tags_registers(struct mlx5_dev_ctx_shared *sh)
@@ -39 +40 @@
-@@ -1649,9 +1650,14 @@ mlx5_init_hws_flow_tags_registers(struct mlx5_dev_ctx_shared *sh)
+@@ -1650,9 +1651,14 @@ mlx5_init_hws_flow_tags_registers(struct mlx5_dev_ctx_shared *sh)
@@ -59 +60 @@
-index 6254857301..20d38ce414 100644
+index 126f0475d5..5601abf90d 100644
@@ -62 +63 @@
-@@ -9657,4 +9657,17 @@ flow_hw_destroy_send_to_kernel_action(struct mlx5_priv *priv)
+@@ -9500,4 +9500,17 @@ flow_hw_destroy_send_to_kernel_action(struct mlx5_priv *priv)
@@ -80 +81 @@
-@@ -12198,7 +12211,12 @@ __flow_hw_configure(struct rte_eth_dev *dev,
+@@ -11966,7 +11979,12 @@ __flow_hw_configure(struct rte_eth_dev *dev,