patch 'net/mlx5/hws: fix crash using represented port without ID' has been queued to stable release 23.11.4

[Xueming Li <xuemingl@nvidia.com>]

Hi,

FYI, your patch has been queued to stable release 23.11.4

Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet.
It will be pushed if I get no objections before 04/10/25. So please
shout if anyone has objections.

Also note that after the patch there's a diff of the upstream commit vs the
patch applied to the branch. This will indicate if there was any rebasing
needed to apply to the stable branch. If there were code changes for rebasing
(ie: not only metadata diffs), please double check that the rebase was
correctly done.

Queued patches are on a temporary branch at:
https://git.dpdk.org/dpdk-stable/log/?h=23.11-staging

This queued commit can be viewed at:
https://git.dpdk.org/dpdk-stable/commit/?h=23.11-staging&id=6135fd39aa5d5fb6dc1f2cafc46d9ab4bcbba3ae

Thanks.

Xueming Li <xuemingl@nvidia.com>

---
From 6135fd39aa5d5fb6dc1f2cafc46d9ab4bcbba3ae Mon Sep 17 00:00:00 2001
From: Maayan Kashani <mkashani@nvidia.com>
Date: Thu, 27 Feb 2025 12:33:29 +0200
Subject: [PATCH] net/mlx5/hws: fix crash using represented port without ID
Cc: Xueming Li <xuemingl@nvidia.com>

[ upstream commit 1de93ca6aee6acb785c8080f84da26b09835af0f ]

For non-template API on top of HWS, when trying to use
represented-port item w/o setting the ethdev_port_id,
it crashes.

Added default values to match the case for SWS.
Default port is now eswitch manager id.

Fixes: c55c2bf35333 ("net/mlx5/hws: add definer layer")

Signed-off-by: Maayan Kashani <mkashani@nvidia.com>
Acked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>
---
 drivers/net/mlx5/hws/mlx5dr_definer.c | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c
index 93e15122ed..14caae6563 100644
--- a/drivers/net/mlx5/hws/mlx5dr_definer.c
+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c
@@ -592,10 +592,11 @@ mlx5dr_definer_vport_set(struct mlx5dr_definer_fc *fc,
 			 uint8_t *tag)
 {
 	const struct rte_flow_item_ethdev *v = item_spec;
-	const struct flow_hw_port_info *port_info;
+	const struct flow_hw_port_info *port_info = NULL;
 	uint32_t regc_value;
 
-	port_info = flow_hw_conv_port_id(v->port_id);
+	if (v)
+		port_info = flow_hw_conv_port_id(v->port_id);
 	if (unlikely(!port_info))
 		regc_value = BAD_PORT;
 	else
@@ -1326,11 +1327,12 @@ mlx5dr_definer_conv_item_port(struct mlx5dr_definer_conv_data *cd,
 			      int item_idx)
 {
 	struct mlx5dr_cmd_query_caps *caps = cd->ctx->caps;
-	const struct rte_flow_item_ethdev *m = item->mask;
+	uint16_t port_id = item->mask ?
+			   ((const struct rte_flow_item_ethdev *)(item->mask))->port_id : 0;
 	struct mlx5dr_definer_fc *fc;
 	uint8_t bit_offset = 0;
 
-	if (m->port_id) {
+	if (port_id) {
 		if (!caps->wire_regc_mask) {
 			DR_LOG(ERR, "Port ID item not supported, missing wire REGC mask");
 			rte_errno = ENOTSUP;
@@ -1347,10 +1349,6 @@ mlx5dr_definer_conv_item_port(struct mlx5dr_definer_conv_data *cd,
 		DR_CALC_SET_HDR(fc, registers, register_c_0);
 		fc->bit_off = bit_offset;
 		fc->bit_mask = caps->wire_regc_mask >> bit_offset;
-	} else {
-		DR_LOG(ERR, "Pord ID item mask must specify ID mask");
-		rte_errno = EINVAL;
-		return rte_errno;
 	}
 
 	return 0;
-- 
2.34.1

---
  Diff of the applied patch vs upstream commit (please double-check if non-empty:
---
--- -	2025-04-08 15:39:07.067622112 +0800
+++ 0039-net-mlx5-hws-fix-crash-using-represented-port-withou.patch	2025-04-08 15:39:06.006436555 +0800
@@ -1 +1 @@
-From 1de93ca6aee6acb785c8080f84da26b09835af0f Mon Sep 17 00:00:00 2001
+From 6135fd39aa5d5fb6dc1f2cafc46d9ab4bcbba3ae Mon Sep 17 00:00:00 2001
@@ -4,0 +5,3 @@
+Cc: Xueming Li <xuemingl@nvidia.com>
+
+[ upstream commit 1de93ca6aee6acb785c8080f84da26b09835af0f ]
@@ -14 +16,0 @@
-Cc: stable@dpdk.org
@@ -23 +25 @@
-index 98d670fc1c..a4b9306d2b 100644
+index 93e15122ed..14caae6563 100644
@@ -26 +28 @@
-@@ -772,10 +772,11 @@ mlx5dr_definer_vport_set(struct mlx5dr_definer_fc *fc,
+@@ -592,10 +592,11 @@ mlx5dr_definer_vport_set(struct mlx5dr_definer_fc *fc,
@@ -34 +36 @@
--	port_info = flow_hw_conv_port_id(fc->dr_ctx, v->port_id);
+-	port_info = flow_hw_conv_port_id(v->port_id);
@@ -36 +38 @@
-+		port_info = flow_hw_conv_port_id(fc->dr_ctx, v->port_id);
++		port_info = flow_hw_conv_port_id(v->port_id);
@@ -40 +42 @@
-@@ -1585,10 +1586,11 @@ mlx5dr_definer_conv_item_port(struct mlx5dr_definer_conv_data *cd,
+@@ -1326,11 +1327,12 @@ mlx5dr_definer_conv_item_port(struct mlx5dr_definer_conv_data *cd,
@@ -47,0 +50 @@
+ 	uint8_t bit_offset = 0;
@@ -54,4 +57,4 @@
-@@ -1603,10 +1605,6 @@ mlx5dr_definer_conv_item_port(struct mlx5dr_definer_conv_data *cd,
- 		fc->bit_off = rte_ctz32(caps->wire_regc_mask);
- 		fc->bit_mask = caps->wire_regc_mask >> fc->bit_off;
- 		fc->dr_ctx = cd->ctx;
+@@ -1347,10 +1349,6 @@ mlx5dr_definer_conv_item_port(struct mlx5dr_definer_conv_data *cd,
+ 		DR_CALC_SET_HDR(fc, registers, register_c_0);
+ 		fc->bit_off = bit_offset;
+ 		fc->bit_mask = caps->wire_regc_mask >> bit_offset;