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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.161 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.161) by BN1PEPF0000468A.mail.protection.outlook.com (10.167.243.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8632.13 via Frontend Transport; Tue, 8 Apr 2025 08:12:11 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.67) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Tue, 8 Apr 2025 01:11:59 -0700 Received: from nvidia.com (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.14; Tue, 8 Apr 2025 01:11:56 -0700 From: Xueming Li To: Maayan Kashani CC: Xueming Li , Dariusz Sosnowski , dpdk stable Subject: patch 'net/mlx5/hws: fix GTP flags matching' has been queued to stable release 23.11.4 Date: Tue, 8 Apr 2025 16:10:44 +0800 Message-ID: <20250408081054.375502-6-xuemingl@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250408081054.375502-1-xuemingl@nvidia.com> References: <20250218123523.36836-1-xuemingl@nvidia.com> <20250408081054.375502-1-xuemingl@nvidia.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.35] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0000468A:EE_|IA0PR12MB8255:EE_ X-MS-Office365-Filtering-Correlation-Id: a8760dbd-a170-4e7d-65a6-08dd76751054 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE; SFS:(13230040)(376014)(36860700013)(1800799024)(82310400026)(13003099007); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Apr 2025 08:12:11.1808 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a8760dbd-a170-4e7d-65a6-08dd76751054 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000468A.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8255 X-BeenThere: stable@dpdk.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: patches for DPDK stable branches List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: stable-bounces@dpdk.org Hi, FYI, your patch has been queued to stable release 23.11.4 Note it hasn't been pushed to http://dpdk.org/browse/dpdk-stable yet. It will be pushed if I get no objections before 04/10/25. So please shout if anyone has objections. Also note that after the patch there's a diff of the upstream commit vs the patch applied to the branch. This will indicate if there was any rebasing needed to apply to the stable branch. If there were code changes for rebasing (ie: not only metadata diffs), please double check that the rebase was correctly done. Queued patches are on a temporary branch at: https://git.dpdk.org/dpdk-stable/log/?h=23.11-staging This queued commit can be viewed at: https://git.dpdk.org/dpdk-stable/commit/?h=23.11-staging&id=3003a65e36ba351e84d34da5742f15f97aa5931c Thanks. Xueming Li --- >From 3003a65e36ba351e84d34da5742f15f97aa5931c Mon Sep 17 00:00:00 2001 From: Maayan Kashani Date: Thu, 27 Feb 2025 12:49:40 +0200 Subject: [PATCH] net/mlx5/hws: fix GTP flags matching Cc: Xueming Li [ upstream commit a31da10717be6a79877621e94eeb003f547c5f88 ] Support GTP flags in non-template on top of HWS. Currently, only extension flag was supported, Added support to all bits under v_pt_rsv_flags. Fixes: c55c2bf35333 ("net/mlx5/hws: add definer layer") Signed-off-by: Maayan Kashani Acked-by: Dariusz Sosnowski --- drivers/net/mlx5/hws/mlx5dr_definer.c | 12 ++++++------ drivers/net/mlx5/hws/mlx5dr_definer.h | 18 ++++++++++++------ 2 files changed, 18 insertions(+), 12 deletions(-) diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c index 14caae6563..69a99d6785 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.c +++ b/drivers/net/mlx5/hws/mlx5dr_definer.c @@ -166,7 +166,7 @@ struct mlx5dr_definer_conv_data { X(SET, gtp_udp_port, UDP_GTPU_PORT, rte_flow_item_gtp) \ X(SET_BE32, gtp_teid, v->hdr.teid, rte_flow_item_gtp) \ X(SET, gtp_msg_type, v->hdr.msg_type, rte_flow_item_gtp) \ - X(SET, gtp_ext_flag, !!v->hdr.gtp_hdr_info, rte_flow_item_gtp) \ + X(SET, gtp_flags, v->hdr.gtp_hdr_info, rte_flow_item_gtp) \ X(SET, gtp_next_ext_hdr, GTP_PDU_SC, rte_flow_item_gtp_psc) \ X(SET, gtp_ext_hdr_pdu, v->hdr.type, rte_flow_item_gtp_psc) \ X(SET, gtp_ext_hdr_qfi, v->hdr.qfi, rte_flow_item_gtp_psc) \ @@ -1204,7 +1204,7 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd, if (!m) return 0; - if (m->hdr.plen || m->hdr.gtp_hdr_info & ~MLX5DR_DEFINER_GTP_EXT_HDR_BIT) { + if (m->msg_len) { rte_errno = ENOTSUP; return rte_errno; } @@ -1226,11 +1226,11 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd, rte_errno = ENOTSUP; return rte_errno; } - fc = &cd->fc[MLX5DR_DEFINER_FNAME_GTP_EXT_FLAG]; + fc = &cd->fc[MLX5DR_DEFINER_FNAME_GTP_FLAGS]; fc->item_idx = item_idx; - fc->tag_set = &mlx5dr_definer_gtp_ext_flag_set; - fc->bit_mask = __mlx5_mask(header_gtp, ext_hdr_flag); - fc->bit_off = __mlx5_dw_bit_off(header_gtp, ext_hdr_flag); + fc->tag_set = &mlx5dr_definer_gtp_flags_set; + fc->bit_mask = __mlx5_mask(header_gtp, v_pt_rsv_flags); + fc->bit_off = __mlx5_dw_bit_off(header_gtp, v_pt_rsv_flags); fc->byte_off = caps->format_select_gtpu_dw_0 * DW_SIZE; } diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h index 6f1c99e37a..5775c47fc3 100644 --- a/drivers/net/mlx5/hws/mlx5dr_definer.h +++ b/drivers/net/mlx5/hws/mlx5dr_definer.h @@ -77,6 +77,7 @@ enum mlx5dr_definer_fname { MLX5DR_DEFINER_FNAME_GTP_TEID, MLX5DR_DEFINER_FNAME_GTP_MSG_TYPE, MLX5DR_DEFINER_FNAME_GTP_EXT_FLAG, + MLX5DR_DEFINER_FNAME_GTP_FLAGS, MLX5DR_DEFINER_FNAME_GTP_NEXT_EXT_HDR, MLX5DR_DEFINER_FNAME_GTP_EXT_HDR_PDU, MLX5DR_DEFINER_FNAME_GTP_EXT_HDR_QFI, @@ -534,12 +535,17 @@ enum mlx5dr_definer_gtp { }; struct mlx5_ifc_header_gtp_bits { - u8 version[0x3]; - u8 proto_type[0x1]; - u8 reserved1[0x1]; - u8 ext_hdr_flag[0x1]; - u8 seq_num_flag[0x1]; - u8 pdu_flag[0x1]; + union { + u8 v_pt_rsv_flags[0x8]; + struct { + u8 version[0x3]; + u8 proto_type[0x1]; + u8 reserved1[0x1]; + u8 ext_hdr_flag[0x1]; + u8 seq_num_flag[0x1]; + u8 pdu_flag[0x1]; + }; + }; u8 msg_type[0x8]; u8 msg_len[0x8]; u8 teid[0x20]; -- 2.34.1 --- Diff of the applied patch vs upstream commit (please double-check if non-empty: --- --- - 2025-04-08 15:39:07.092159205 +0800 +++ 0040-net-mlx5-hws-fix-GTP-flags-matching.patch 2025-04-08 15:39:06.006436555 +0800 @@ -1 +1 @@ -From a31da10717be6a79877621e94eeb003f547c5f88 Mon Sep 17 00:00:00 2001 +From 3003a65e36ba351e84d34da5742f15f97aa5931c Mon Sep 17 00:00:00 2001 @@ -4,0 +5,3 @@ +Cc: Xueming Li + +[ upstream commit a31da10717be6a79877621e94eeb003f547c5f88 ] @@ -11 +13,0 @@ -Cc: stable@dpdk.org @@ -21 +23 @@ -index a4b9306d2b..5272119bcb 100644 +index 14caae6563..69a99d6785 100644 @@ -24 +26 @@ -@@ -199,7 +199,7 @@ struct mlx5dr_definer_conv_data { +@@ -166,7 +166,7 @@ struct mlx5dr_definer_conv_data { @@ -33 +35 @@ -@@ -1463,7 +1463,7 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd, +@@ -1204,7 +1204,7 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd, @@ -42 +44 @@ -@@ -1485,11 +1485,11 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd, +@@ -1226,11 +1226,11 @@ mlx5dr_definer_conv_item_gtp(struct mlx5dr_definer_conv_data *cd, @@ -59 +61 @@ -index 092b1b3b10..d0c99399ae 100644 +index 6f1c99e37a..5775c47fc3 100644 @@ -62 +64 @@ -@@ -110,6 +110,7 @@ enum mlx5dr_definer_fname { +@@ -77,6 +77,7 @@ enum mlx5dr_definer_fname { @@ -70 +72 @@ -@@ -606,12 +607,17 @@ enum mlx5dr_definer_gtp { +@@ -534,12 +535,17 @@ enum mlx5dr_definer_gtp {